iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-1/+0
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-4/+4
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-1/+1
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-2/+2
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*	More RTLIL::Cell API usage cleanups	Clifford Wolf	2014-07-26	1	-1/+1
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*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	1	-1/+1
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-4/+4
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at\("([^"])"\)/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-4/+4
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*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-9/+7
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*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-11/+11
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-11/+11
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*	Added "top" attribute to mark top module in hierarchy	Clifford Wolf	2013-11-24	1	-0/+5
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*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22	1	-2/+2
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*	Silenced a gcc warning in spice backend	Clifford Wolf	2013-11-09	1	-1/+1
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*	Write yosys version to output files	Clifford Wolf	2013-11-03	1	-4/+1
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*	Fixed handling of boolean attributes (backends)	Clifford Wolf	2013-10-24	1	-1/+1
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*	A couple of small fixes in SPICE backend	Clifford Wolf	2013-09-15	1	-6/+18
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*	Added spice testbench to techlibs/cmos	Clifford Wolf	2013-09-14	1	-3/+0
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*	Added spice backend	Clifford Wolf	2013-09-14	2	-0/+228