| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 | 2 | -4/+8 |
| * | Added wire->upto flag for signals such as "wire [0:7] x;" | Clifford Wolf | 2014-07-28 | 1 | -0/+2 |
| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 1 | -3/+2 |
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -2/+2 |
| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -2/+2 |
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -2/+2 |
| * | Various RTLIL::SigSpec related code cleanups | Clifford Wolf | 2014-07-25 | 1 | -2/+2 |
| * | Replaced more old SigChunk programming patterns | Clifford Wolf | 2014-07-24 | 1 | -1/+1 |
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -4/+4 |
| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -4/+4 |
| * | Added "autoidx" statement to ilang file format | Clifford Wolf | 2014-07-21 | 1 | -1/+14 |
| * | Merged OSX fixes from Siesh1oo with some modifications | Clifford Wolf | 2014-03-13 | 1 | -0/+1 |
| * | Added support for dump -append | Clifford Wolf | 2014-02-04 | 1 | -3/+12 |
| * | Updated manual/command-reference-manual.tex | Clifford Wolf | 2013-12-28 | 1 | -1/+1 |
| * | Replaced signed_parameters API with CONST_FLAG_SIGNED | Clifford Wolf | 2013-12-04 | 1 | -1/+1 |
| * | Replaced RTLIL::Const::str with generic decoder method | Clifford Wolf | 2013-12-04 | 1 | -8/+11 |
| * | Added dump -m and -n options | Clifford Wolf | 2013-11-29 | 2 | -54/+89 |
| * | Added support for signed parameters in ilang | Clifford Wolf | 2013-11-24 | 1 | -1/+1 |
| * | Remove auto_wire framework (smarter than the verilog standard) | Clifford Wolf | 2013-11-24 | 1 | -2/+0 |
| * | Major improvements in mem2reg and added "init" sync rules | Clifford Wolf | 2013-11-21 | 1 | -0/+1 |
| * | Write yosys version to output files | Clifford Wolf | 2013-11-03 | 1 | -0/+1 |
| * | Added -selected option to various backends | Clifford Wolf | 2013-09-03 | 1 | -3/+20 |
| * | Fixed generation of newlines in "dump" output | Clifford Wolf | 2013-06-10 | 1 | -3/+4 |
| * | Added "dump" command (part ilang backend) | Clifford Wolf | 2013-06-02 | 2 | -13/+103 |
| * | Added more help messages | Clifford Wolf | 2013-03-01 | 1 | -1/+11 |
| * | initial import | Clifford Wolf | 2013-01-05 | 3 | -0/+356 |
