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path: root/backends/cxxrtl/cxxrtl.h
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* Add support for GHDL modfloor operatorMichael Nolan2022-07-051-0/+21
* Add $bmux and $demux cells.Marcelina Kościelnicka2022-01-281-0/+36
* cxxrtl: preserve interior memory pointers across reset.Catherine2021-12-111-21/+3
* cxxrtl: use unique_ptr<value<>[]> to store memory contents.whitequark2021-12-111-16/+16
* cxxrtl: add debug_item::{get,set}.whitequark2021-07-181-0/+16
* cxxrtl: do not use `->template` for non-dependent names.whitequark2021-01-261-8/+8
* cxxrtl: speed up bit repeats (sign extends, etc).whitequark2020-12-211-0/+8
* cxxrtl: disable optimization of debug_items().whitequark2020-12-151-3/+14
* cxxrtl: implement debug information outlining.whitequark2020-12-141-5/+36
* cxxrtl: don't overwrite buffered inputs.whitequark2020-12-111-1/+1
* Merge pull request #2468 from whitequark/cxxrtl-assertwhitequark2020-12-021-0/+14
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| * cxxrtl: use CXXRTL_ASSERT for RTL contract violations instead of assert.whitequark2020-12-021-0/+14
* | cxxrtl: provide a way to perform unobtrusive power-on reset.whitequark2020-12-021-3/+26
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* cxxrtl: expose driver kind in debug information.whitequark2020-09-021-4/+7
* cxxrtl: expose port direction in debug information.whitequark2020-09-021-4/+18
* cxxrtl.h: Fix incorrect CarryOut in alu()Andy Knowles2020-08-121-8/+3
* cxxrtl.h: Fix incorrect CarryOut in alu when Bits % 32 != 0 && Invert == FalseAndy Knowles2020-08-121-2/+8
* cxxrtl: add .get() and .set() accessors on value<> and wire<>.whitequark2020-06-191-6/+47
* Merge pull request #2159 from MerryMage/cxxrtl-mulwhitequark2020-06-151-17/+22
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| * cxxrtl: Implement chunk-wise multiplicationMerryMage2020-06-151-17/+22
* | Merge pull request #2158 from miek/sshr-sign-extensionwhitequark2020-06-151-2/+4
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| * cxxrtl: fix sshr sign-extension.Mike Walters2020-06-151-2/+4
* | Merge pull request #2151 from whitequark/cxxrtl-fix-rzextwhitequark2020-06-131-2/+2
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| * cxxrtl: fix rzext().whitequark2020-06-131-2/+2
* | Merge pull request #2145 from whitequark/cxxrtl-splitnetswhitequark2020-06-131-37/+80
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| * | cxxrtl: handle multipart signals.whitequark2020-06-111-1/+32
| * | cxxrtl: expose RTLIL::{Wire,Memory}->start_offset in debug info.whitequark2020-06-111-36/+48
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* / cxxrtl: always inline internal cells and slice/concat operations.whitequark2020-06-131-4/+108
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* Merge pull request #2141 from whitequark/cxxrtl-cxx11whitequark2020-06-101-5/+6
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| * cxxrtl: fix a few gcc warnings.whitequark2020-06-101-5/+6
* | cxxrtl: disambiguate values/wires and their aliases in debug info.whitequark2020-06-101-1/+28
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* cxxrtl: ignore cell input signedness when it is irrelevant.whitequark2020-06-091-57/+19
* cxxrtl: emit debug information for constant wires.whitequark2020-06-081-0/+11
* cxxrtl: add a C API for writing VCD dumps.whitequark2020-06-071-0/+2
* cxxrtl: add a C API for driving and introspecting designs.whitequark2020-06-061-29/+46
* cxxrtl: generate debug information for non-localized public wires.whitequark2020-06-061-1/+45
* cxxrtl: fix implementation of $sshr cell.whitequark2020-06-051-1/+1
* cxxrtl: keep the memory write queue sorted on insertion.Asu2020-04-221-3/+5
* cxxrtl: use one delta cycle for immediately converging netlists.whitequark2020-04-211-3/+4
* cxxrtl: provide attributes to black box factories, too.whitequark2020-04-191-10/+10
* cxxrtl: add simple black box support.whitequark2020-04-181-0/+53
* cxxrtl: make ROMs writable, document memory::operator[].whitequark2020-04-161-2/+5
* write_cxxrtl: improve writable memory handling.whitequark2020-04-091-39/+64
* write_cxxrtl: avoid undefined behavior on out-of-bounds memory access.whitequark2020-04-091-8/+13
* write_cxxrtl: statically schedule comb logic and localize wires.whitequark2020-04-091-0/+4
* write_cxxrtl: new backend.whitequark2020-04-091-0/+1104
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