iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	cxxrtl: expose driver kind in debug information.	whitequark	2020-09-02	1	-4/+7
*	cxxrtl: expose port direction in debug information.	whitequark	2020-09-02	1	-4/+18
*	cxxrtl.h: Fix incorrect CarryOut in alu()	Andy Knowles	2020-08-12	1	-8/+3
*	cxxrtl.h: Fix incorrect CarryOut in alu when Bits % 32 != 0 && Invert == False	Andy Knowles	2020-08-12	1	-2/+8
*	cxxrtl: add .get() and .set() accessors on value<> and wire<>.	whitequark	2020-06-19	1	-6/+47
*	Merge pull request #2159 from MerryMage/cxxrtl-mul	whitequark	2020-06-15	1	-17/+22
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\| *	cxxrtl: Implement chunk-wise multiplication	MerryMage	2020-06-15	1	-17/+22
* \|	Merge pull request #2158 from miek/sshr-sign-extension	whitequark	2020-06-15	1	-2/+4
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\| *	cxxrtl: fix sshr sign-extension.	Mike Walters	2020-06-15	1	-2/+4
* \|	Merge pull request #2151 from whitequark/cxxrtl-fix-rzext	whitequark	2020-06-13	1	-2/+2
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\| *	cxxrtl: fix rzext().	whitequark	2020-06-13	1	-2/+2
* \|	Merge pull request #2145 from whitequark/cxxrtl-splitnets	whitequark	2020-06-13	1	-37/+80
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\| * \|	cxxrtl: handle multipart signals.	whitequark	2020-06-11	1	-1/+32
\| * \|	cxxrtl: expose RTLIL::{Wire,Memory}->start_offset in debug info.	whitequark	2020-06-11	1	-36/+48
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* /	cxxrtl: always inline internal cells and slice/concat operations.	whitequark	2020-06-13	1	-4/+108
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*	Merge pull request #2141 from whitequark/cxxrtl-cxx11	whitequark	2020-06-10	1	-5/+6
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\| *	cxxrtl: fix a few gcc warnings.	whitequark	2020-06-10	1	-5/+6
* \|	cxxrtl: disambiguate values/wires and their aliases in debug info.	whitequark	2020-06-10	1	-1/+28
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*	cxxrtl: ignore cell input signedness when it is irrelevant.	whitequark	2020-06-09	1	-57/+19
*	cxxrtl: emit debug information for constant wires.	whitequark	2020-06-08	1	-0/+11
*	cxxrtl: add a C API for writing VCD dumps.	whitequark	2020-06-07	1	-0/+2
*	cxxrtl: add a C API for driving and introspecting designs.	whitequark	2020-06-06	1	-29/+46
*	cxxrtl: generate debug information for non-localized public wires.	whitequark	2020-06-06	1	-1/+45
*	cxxrtl: fix implementation of $sshr cell.	whitequark	2020-06-05	1	-1/+1
*	cxxrtl: keep the memory write queue sorted on insertion.	Asu	2020-04-22	1	-3/+5
*	cxxrtl: use one delta cycle for immediately converging netlists.	whitequark	2020-04-21	1	-3/+4
*	cxxrtl: provide attributes to black box factories, too.	whitequark	2020-04-19	1	-10/+10
*	cxxrtl: add simple black box support.	whitequark	2020-04-18	1	-0/+53
*	cxxrtl: make ROMs writable, document memory::operator[].	whitequark	2020-04-16	1	-2/+5
*	write_cxxrtl: improve writable memory handling.	whitequark	2020-04-09	1	-39/+64
*	write_cxxrtl: avoid undefined behavior on out-of-bounds memory access.	whitequark	2020-04-09	1	-8/+13
*	write_cxxrtl: statically schedule comb logic and localize wires.	whitequark	2020-04-09	1	-0/+4
*	write_cxxrtl: new backend.	whitequark	2020-04-09	1	-0/+1104