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* Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-061-0/+7
* Fix handling of offset and upto module ports in write_blif, fixes #1040Clifford Wolf2019-05-251-6/+20
* Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-181-3/+3
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Add "write_blif -inames -iattr"Clifford Wolf2018-04-151-22/+46
* Add $_ANDNOT_ and $_ORNOT_ gatesClifford Wolf2017-05-171-0/+12
* Added wire start_offset and upto handling BLIF back-endClifford Wolf2016-11-231-1/+1
* Use init value "2" for all uninitialized FFs in BLIF back-endClifford Wolf2016-10-181-4/+1
* Added $ff and $_FF_ cell typesClifford Wolf2016-10-121-0/+6
* Restored blif "-true - .." behavior, use "-true + .." for eddiehung-vtr behaviorClifford Wolf2016-07-081-13/+15
* In BLIF, a .names without entries already always outputs 0Clifford Wolf2016-07-081-11/+0
* Merge branch 'yosys-0.5-vtr' of https://github.com/eddiehung/yosys into eddie...Clifford Wolf2016-07-081-2/+19
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| * Fix for all zero maskeddiehung2015-05-031-0/+11
| * Escape '<' and '>' some moreeddiehung2015-05-031-1/+1
| * For vtr, escape angle brackets as welleddiehung2015-04-281-1/+1
| * blifwriter: write out .names for true/false/undef type == '-'eddiehung2015-04-281-0/+6
* | Added $sop support to BLIF back-endClifford Wolf2016-06-181-2/+29
* | Added "write_blif -noalias"Clifford Wolf2016-05-061-6/+26
* | Added support for "active high" and "active low" latches in BLIF back-endClifford Wolf2016-04-221-0/+12
* | Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* | Fixed some typosClifford Wolf2016-04-051-1/+1
* | Added "write_blif -cname" modeClifford Wolf2016-01-061-1/+12
* | Improvements in BLIF back-endClifford Wolf2015-07-291-5/+84
* | Fixed trailing whitespacesClifford Wolf2015-07-021-2/+2
* | Fixed cstr_buf for std::string with small string optimizationClifford Wolf2015-06-111-1/+1
* | Improvements in BLIF front-endClifford Wolf2015-05-241-0/+1
* | Added write_blif -attrClifford Wolf2015-03-021-18/+33
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* Fixed another bug in write_blif handling of $lut cellsClifford Wolf2014-12-191-1/+1
* Fixed writing of $lut cells in BLIF backendClifford Wolf2014-12-171-7/+7
* Added "write_blif -undef" and support for special "-" true/false/undef typeClifford Wolf2014-12-141-13/+33
* Added "write_blif -blackbox"Clifford Wolf2014-12-141-2/+16
* Added "blif -unbuf" featureClifford Wolf2014-12-141-0/+19
* namespace YosysClifford Wolf2014-09-271-0/+4
* Corrected spelling mistakes found by lintianRuben Undheim2014-09-061-1/+1
* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-231-48/+48
* Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-151-2/+2
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-151-1/+1
* No implicit conversion from IdString to anything elseClifford Wolf2014-08-021-1/+1
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-1/+1
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-10/+10
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-1/+0
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-4/+4
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-1/+1
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-12/+12
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-12/+12
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-241-8/+6
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-231-1/+0
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-231-2/+2
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-231-2/+2