aboutsummaryrefslogtreecommitdiffstats
path: root/backends/blif
diff options
context:
space:
mode:
authorClifford Wolf <clifford@clifford.at>2019-04-18 17:42:12 +0200
committerClifford Wolf <clifford@clifford.at>2019-04-18 17:45:47 +0200
commitf4abc21d8ad79621cc24852bd76abf40a9d9f702 (patch)
tree016692552e9880b3e37a715b53f45db707c83a91 /backends/blif
parentea8ac0aaad3a1f89ead8eb44b2fef5927f29a099 (diff)
downloadyosys-f4abc21d8ad79621cc24852bd76abf40a9d9f702.tar.gz
yosys-f4abc21d8ad79621cc24852bd76abf40a9d9f702.tar.bz2
yosys-f4abc21d8ad79621cc24852bd76abf40a9d9f702.zip
Add "whitebox" attribute, add "read_verilog -wb"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'backends/blif')
-rw-r--r--backends/blif/blif.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index 0db5ff27c..b6dbd84cb 100644
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -140,7 +140,7 @@ struct BlifDumper
return "subckt";
if (!design->modules_.count(RTLIL::escape_id(cell_type)))
return "gate";
- if (design->modules_.at(RTLIL::escape_id(cell_type))->get_bool_attribute("\\blackbox"))
+ if (design->modules_.at(RTLIL::escape_id(cell_type))->get_blackbox_attribute())
return "gate";
return "subckt";
}
@@ -196,7 +196,7 @@ struct BlifDumper
}
f << stringf("\n");
- if (module->get_bool_attribute("\\blackbox")) {
+ if (module->get_blackbox_attribute()) {
f << stringf(".blackbox\n");
f << stringf(".end\n");
return;
@@ -640,7 +640,7 @@ struct BlifBackend : public Backend {
for (auto module_it : design->modules_)
{
RTLIL::Module *module = module_it.second;
- if (module->get_bool_attribute("\\blackbox") && !config.blackbox_mode)
+ if (module->get_blackbox_attribute() && !config.blackbox_mode)
continue;
if (module->processes.size() != 0)