iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fix handling of offset and upto module ports in write_blif, fixes #1040	Clifford Wolf	2019-05-25	1	-6/+20
*	Add "whitebox" attribute, add "read_verilog -wb"	Clifford Wolf	2019-04-18	1	-3/+3
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
*	Add "write_blif -inames -iattr"	Clifford Wolf	2018-04-15	1	-22/+46
*	Add $_ANDNOT_ and $_ORNOT_ gates	Clifford Wolf	2017-05-17	1	-0/+12
*	Added wire start_offset and upto handling BLIF back-end	Clifford Wolf	2016-11-23	1	-1/+1
*	Use init value "2" for all uninitialized FFs in BLIF back-end	Clifford Wolf	2016-10-18	1	-4/+1
*	Added $ff and $_FF_ cell types	Clifford Wolf	2016-10-12	1	-0/+6
*	Restored blif "-true - .." behavior, use "-true + .." for eddiehung-vtr behavior	Clifford Wolf	2016-07-08	1	-13/+15
*	In BLIF, a .names without entries already always outputs 0	Clifford Wolf	2016-07-08	1	-11/+0
*	Merge branch 'yosys-0.5-vtr' of https://github.com/eddiehung/yosys into eddie...	Clifford Wolf	2016-07-08	1	-2/+19
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\| *	Fix for all zero mask	eddiehung	2015-05-03	1	-0/+11
\| *	Escape '<' and '>' some more	eddiehung	2015-05-03	1	-1/+1
\| *	For vtr, escape angle brackets as well	eddiehung	2015-04-28	1	-1/+1
\| *	blifwriter: write out .names for true/false/undef type == '-'	eddiehung	2015-04-28	1	-0/+6
* \|	Added $sop support to BLIF back-end	Clifford Wolf	2016-06-18	1	-2/+29
* \|	Added "write_blif -noalias"	Clifford Wolf	2016-05-06	1	-6/+26
* \|	Added support for "active high" and "active low" latches in BLIF back-end	Clifford Wolf	2016-04-22	1	-0/+12
* \|	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
* \|	Fixed some typos	Clifford Wolf	2016-04-05	1	-1/+1
* \|	Added "write_blif -cname" mode	Clifford Wolf	2016-01-06	1	-1/+12
* \|	Improvements in BLIF back-end	Clifford Wolf	2015-07-29	1	-5/+84
* \|	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-2/+2
* \|	Fixed cstr_buf for std::string with small string optimization	Clifford Wolf	2015-06-11	1	-1/+1
* \|	Improvements in BLIF front-end	Clifford Wolf	2015-05-24	1	-0/+1
* \|	Added write_blif -attr	Clifford Wolf	2015-03-02	1	-18/+33
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*	Fixed another bug in write_blif handling of $lut cells	Clifford Wolf	2014-12-19	1	-1/+1
*	Fixed writing of $lut cells in BLIF backend	Clifford Wolf	2014-12-17	1	-7/+7
*	Added "write_blif -undef" and support for special "-" true/false/undef type	Clifford Wolf	2014-12-14	1	-13/+33
*	Added "write_blif -blackbox"	Clifford Wolf	2014-12-14	1	-2/+16
*	Added "blif -unbuf" feature	Clifford Wolf	2014-12-14	1	-0/+19
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-0/+4
*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06	1	-1/+1
*	Changed backend-api from FILE to std::ostream	Clifford Wolf	2014-08-23	1	-48/+48
*	Renamed $lut ports to follow A-Y naming scheme	Clifford Wolf	2014-08-15	1	-2/+2
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15	1	-1/+1
*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	1	-1/+1
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-1/+1
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-10/+10
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-1/+0
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-4/+4
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-1/+1
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-12/+12
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-12/+12
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-8/+6
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-1/+0
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-2/+2
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-2/+2
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-12/+12