iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	write_xaiger: inherit port ordering from original module	Eddie Hung	2019-12-27	1	-5/+16
*	Revert "Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup"	Eddie Hung	2019-12-27	1	-19/+27
*	Merge branch 'master' of github.com:YosysHQ/yosys	Eddie Hung	2019-12-27	1	-27/+19
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\| *	Revert "write_xaiger: only instantiate each whitebox cell type once"	David Shah	2019-12-27	1	-27/+19
* \|	write_xaiger: simplify c{i,o}_bits	Eddie Hung	2019-12-27	1	-12/+6
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*	write_xaiger: only instantiate each whitebox cell type once	Eddie Hung	2019-12-20	1	-19/+27
*	Revert "Optimise write_xaiger"	Eddie Hung	2019-12-20	1	-24/+21
*	Stray newline	Eddie Hung	2019-12-06	1	-1/+0
*	write_xaiger to inst each cell type once, do not call techmap/aigmap	Eddie Hung	2019-12-06	1	-21/+25
*	Revert "Fold loop"	Eddie Hung	2019-11-27	1	-3/+6
*	latch -> box	Eddie Hung	2019-11-26	1	-1/+1
*	Fold loop	Eddie Hung	2019-11-26	1	-6/+3
*	Do not sigmap keep bits inside write_xaiger	Eddie Hung	2019-11-26	1	-1/+1
*	xaiger: do not promote output wires	Eddie Hung	2019-11-26	1	-5/+0
*	Fix write_aiger bug added in 524af21	Clifford Wolf	2019-11-04	1	-0/+3
*	Rename abc_* names/attributes to more precisely be abc9_*	Eddie Hung	2019-10-04	1	-9/+9
*	Merge pull request #1359 from YosysHQ/xc7dsp	Eddie Hung	2019-09-29	1	-8/+8
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\| *	"abc_padding" attr for blackbox outputs that were padded, remove them later	Eddie Hung	2019-09-23	1	-1/+6
\| *	Force $inout.out ports to begin with '$' to indicate internal	Eddie Hung	2019-09-23	1	-1/+1
\| *	When two boxes connect to each other, need not be a (* keep *)	Eddie Hung	2019-09-19	1	-6/+1
* \|	Add aiger and protobuf backends binary support	Miodrag Milanovic	2019-09-28	1	-1/+1
* \|	Support binary files for backends, fixes #1407	Miodrag Milanovic	2019-09-28	1	-1/+1
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*	Add "write_aiger -L"	Clifford Wolf	2019-09-18	1	-5/+16
*	Recognise built-in types (e.g. $_DFF_*)	Eddie Hung	2019-08-30	1	-3/+3
*	Revert "Revert "Fix omode which inserts an output if none exists (otherwise a...	Eddie Hung	2019-08-28	1	-7/+8
*	Revert "Output "h" extension only if boxes"	Eddie Hung	2019-08-28	1	-32/+28
*	Output "h" extension only if boxes	Eddie Hung	2019-08-21	1	-28/+32
*	Revert "Fix omode which inserts an output if none exists (otherwise abc9 brea...	Eddie Hung	2019-08-21	1	-8/+7
*	Fix omode which inserts an output if none exists (otherwise abc9 breaks)	Eddie Hung	2019-08-20	1	-7/+8
*	Revert "Only xaig if GetSize(output_bits) > 0"	Eddie Hung	2019-08-20	1	-149/+147
*	Only xaig if GetSize(output_bits) > 0	Eddie Hung	2019-08-20	1	-147/+149
*	Remove sequential extension	Eddie Hung	2019-08-20	1	-270/+29
*	Do not sigmap!	Eddie Hung	2019-08-20	1	-2/+2
*	Minor refactor	Eddie Hung	2019-08-20	1	-7/+6
*	Output i/o/h extensions even if no boxes or flops	Eddie Hung	2019-08-19	1	-65/+66
*	Add (* abc_arrival *) attribute	Eddie Hung	2019-08-19	1	-9/+66
*	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-08-19	1	-1/+1
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\| *	Fix various NDEBUG compiler warnings, closes #1255	Clifford Wolf	2019-08-13	1	-1/+1
* \|	Use %d	Eddie Hung	2019-08-19	1	-1/+1
* \|	Merge branch 'eddie/abc9_refactor' into xaig_dff	Eddie Hung	2019-08-16	1	-62/+25
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\| * \|	Compute abc_scc_break and move CI/CO outside of each abc9	Eddie Hung	2019-08-16	1	-42/+0
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\| *	Merge pull request #1258 from YosysHQ/eddie/cleanup	Clifford Wolf	2019-08-10	1	-5/+5
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\| \| *	RTLIL::S{0,1} -> State::S{0,1}	Eddie Hung	2019-08-06	1	-5/+5
\| * \|	Run "clean -purge" on holes_module in its own design	Eddie Hung	2019-08-07	1	-6/+11
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\| *	Merge pull request #1238 from mmicko/vsbuild_fix	Clifford Wolf	2019-08-02	1	-1/+1
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\| \| *	Visual Studio build fix	Miodrag Milanovic	2019-07-31	1	-1/+1
\| * \|	Fix formatting for msys2 mingw build using GetSize	Miodrag Milanovic	2019-08-01	1	-6/+6
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* \|	abc_flop to also get topologically sorted	Eddie Hung	2019-07-10	1	-11/+10
* \|	Fix clk_pol for FD*_1	Eddie Hung	2019-07-10	1	-1/+0
* \|	Fix spacing	Eddie Hung	2019-07-10	1	-1/+1