iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Merge pull request #1609 from YosysHQ/clifford/fix1596	Clifford Wolf	2020-01-02	1	-4/+25
\|\
\| *	Always create $shl, $shr, $sshl, $sshr cells with unsigned B inputs	Clifford Wolf	2020-01-02	1	-4/+25
* \|	Merge pull request #1601 from YosysHQ/eddie/synth_retime	Eddie Hung	2020-01-02	13	-48/+52
\|\ \
\| * \|	Update doc that "-retime" calls abc with "-dff -D 1"	Eddie Hung	2019-12-30	11	-12/+12
\| * \|	Disable synth_gowin -abc9 as it offers no advantages yet	Eddie Hung	2019-12-30	1	-12/+12
\| * \|	Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""	Eddie Hung	2019-12-30	11	-13/+13
\| * \|	Revert "ABC to call retime all the time"	Eddie Hung	2019-12-30	1	-11/+15
* \| \|	Merge pull request #1608 from YosysHQ/eddie/ifndef_YOSYS	Eddie Hung	2020-01-02	1	-6/+6
\|\ \ \ \| \|_\|/ \|/\| \|
\| * \|	ifdef __ICARUS__ -> ifndef YOSYS	Eddie Hung	2020-01-01	1	-6/+6
\|/ /
* \|	Merge pull request #1606 from YosysHQ/eddie/improve_tests	Eddie Hung	2020-01-01	10	-19/+20
\|\ \
\| * \|	Revert insertion of 'reg', leave note behind	Eddie Hung	2020-01-01	1	-1/+2
\| * \|	Fix anlogic async flop mapping	Eddie Hung	2020-01-01	1	-8/+8
\| * \|	Do not do call equiv_opt when no sim model exists	Eddie Hung	2019-12-31	2	-4/+4
\| * \|	Fix warnings	Eddie Hung	2019-12-31	2	-2/+2
\| * \|	Call equiv_opt with -multiclock and -assert	Eddie Hung	2019-12-31	5	-5/+5
* \| \|	Merge pull request #1605 from YosysHQ/iopad_fix	Miodrag Milanović	2020-01-01	2	-0/+22
\|\ \ \ \| \|/ / \|/\| \|
\| * \|	Added a test case	Miodrag Milanovic	2020-01-01	1	-0/+19
\| * \|	take skip wire bits into account	Miodrag Milanovic	2020-01-01	1	-0/+3
\|/ /
* \|	Grammar	Eddie Hung	2019-12-30	1	-1/+1
* \|	Update timings for Xilinx S7 cells	Eddie Hung	2019-12-30	1	-15/+35
* \|	Merge pull request #1589 from YosysHQ/iopad_default	Miodrag Milanović	2019-12-30	20	-71/+67
\|\ \ \| \|/ \|/\|
\| *	Fix new tests	Miodrag Milanovic	2019-12-28	3	-6/+6
\| *	Merge remote-tracking branch 'origin/master' into iopad_default	Miodrag Milanovic	2019-12-28	20	-150/+1614
\| \|\
\| * \|	Make test without iopads	Miodrag Milanovic	2019-12-28	17	-51/+51
\| * \|	Revert "Fix xilinx tests, when iopads are default"	Miodrag Milanovic	2019-12-28	16	-40/+40
\| * \|	Addressed review comments	Miodrag Milanovic	2019-12-21	2	-3/+3
\| * \|	iopad no op for compatibility with old scripts	Miodrag Milanovic	2019-12-21	1	-0/+3
\| * \|	Fix xilinx tests, when iopads are default	Miodrag Milanovic	2019-12-21	17	-42/+44
\| * \|	Make iopad option default for all xilinx flows	Miodrag Milanovic	2019-12-21	1	-14/+5
* \| \|	Merge pull request #1599 from YosysHQ/eddie/retry_1588	Eddie Hung	2019-12-30	4	-20/+87
\|\ \ \
\| * \| \|	Add #1598 testcase	Eddie Hung	2019-12-27	3	-0/+48
\| * \| \|	write_xaiger: inherit port ordering from original module	Eddie Hung	2019-12-27	1	-5/+16
\| * \| \|	Revert "Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup"	Eddie Hung	2019-12-27	1	-19/+27
\| \| \|/ \| \|/\|
* \| \|	Merge pull request #1600 from YosysHQ/eddie/cleanup_ecp5	Eddie Hung	2019-12-30	3	-14/+6
\|\ \ \ \| \|/ / \|/\| \|
\| * \|	Update resource count	Eddie Hung	2019-12-28	1	-3/+3
\| * \|	Nitpick cleanup for ecp5	Eddie Hung	2019-12-27	2	-11/+3
\|/ /
* \|	Merge branch 'master' of github.com:YosysHQ/yosys	Eddie Hung	2019-12-27	1	-27/+19
\|\ \
\| * \	Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup	David Shah	2019-12-27	1	-27/+19
\| \|\ \
\| \| * \|	Revert "write_xaiger: only instantiate each whitebox cell type once"	David Shah	2019-12-27	1	-27/+19
\| \|/ /
* / /	write_xaiger: simplify c{i,o}_bits	Eddie Hung	2019-12-27	1	-12/+6
\|/ /
* \|	fixed invalid char	Miodrag Milanovic	2019-12-25	1	-1/+1
* \|	iopadmap: Emit tristate buffers with const OE for some edge cases.	Marcin Kościelnicki	2019-12-25	2	-23/+91
* \|	Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen	Marcin Kościelnicki	2019-12-25	12	-81/+1136
\|\ \
\| * \|	Minor nit fixes	Marcin Kościelnicki	2019-12-25	1	-2/+2
\| * \|	Add DSP cascade tests	Eddie Hung	2019-12-23	1	-0/+89
\| * \|	Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG too	Eddie Hung	2019-12-23	1	-8/+18
\| * \|	Fix CEA/CEB check	Eddie Hung	2019-12-23	1	-2/+2
\| * \|	Fix checking CE[AB] and for direct connections	Eddie Hung	2019-12-23	1	-18/+40
\| * \|	Support unregistered cascades for A and B inputs	Eddie Hung	2019-12-23	1	-47/+74
\| * \|	Add DSP48A* PCOUT -> PCIN cascade support	Eddie Hung	2019-12-23	1	-10/+10