iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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\| *	Merge branch 'master' of github.com:YosysHQ/yosys	Eddie Hung	2019-12-27	1	-27/+19
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\| \| *	Revert "write_xaiger: only instantiate each whitebox cell type once"	David Shah	2019-12-27	1	-27/+19
\| * \|	write_xaiger: simplify c{i,o}_bits	Eddie Hung	2019-12-27	1	-12/+6
\| \|/
\| *	write_xaiger: only instantiate each whitebox cell type once	Eddie Hung	2019-12-20	1	-19/+27
\| *	Revert "Optimise write_xaiger"	Eddie Hung	2019-12-20	1	-24/+21
\| *	Stray newline	Eddie Hung	2019-12-06	1	-1/+0
\| *	write_xaiger to inst each cell type once, do not call techmap/aigmap	Eddie Hung	2019-12-06	1	-21/+25
\| *	Revert "Fold loop"	Eddie Hung	2019-11-27	1	-3/+6
\| *	latch -> box	Eddie Hung	2019-11-26	1	-1/+1
\| *	Fold loop	Eddie Hung	2019-11-26	1	-6/+3
\| *	Do not sigmap keep bits inside write_xaiger	Eddie Hung	2019-11-26	1	-1/+1
\| *	xaiger: do not promote output wires	Eddie Hung	2019-11-26	1	-5/+0
* \|	Add "synth_xilinx -dff" option, cleanup abc9	Eddie Hung	2019-12-30	1	-2/+3
* \|	Really fix it!	Eddie Hung	2019-12-27	1	-10/+7
* \|	write_xaiger: fix arrival times for non boxes	Eddie Hung	2019-12-27	1	-18/+25
* \|	write_xaiger to opt instead of just clean whiteboxes	Eddie Hung	2019-12-23	1	-1/+1
* \|	Cleanup xaiger, remove unnecessary complexity with inout	Eddie Hung	2019-12-17	1	-61/+20
* \|	Do not sigmap	Eddie Hung	2019-12-17	1	-1/+1
* \|	Revert "Use sigmap signal"	Eddie Hung	2019-12-17	1	-1/+1
* \|	Use sigmap signal	Eddie Hung	2019-12-16	1	-1/+1
* \|	Skip $inout transformation if not a PI	Eddie Hung	2019-12-16	1	-3/+5
* \|	Revert "write_xaiger: use sigmap bits more consistently"	Eddie Hung	2019-12-16	1	-4/+5
* \|	write_xaiger: use sigmap bits more consistently	Eddie Hung	2019-12-16	1	-5/+4
* \|	Fix writing non-whole modules, including inouts and keeps	Eddie Hung	2019-12-06	1	-90/+81
* \|	write_xaiger to support part-selected modules again	Eddie Hung	2019-12-05	1	-11/+37
* \|	Cleanup	Eddie Hung	2019-12-03	1	-11/+12
* \|	write_xaiger to consume abc9_init attribute for abc9_flops	Eddie Hung	2019-12-03	1	-34/+28
* \|	Add comment, use sigmap	Eddie Hung	2019-11-27	1	-2/+2
* \|	Revert "Fold loop"	Eddie Hung	2019-11-27	1	-3/+6
* \|	xaiger: do not promote output wires	Eddie Hung	2019-11-26	1	-5/+0
* \|	Fold loop	Eddie Hung	2019-11-25	1	-6/+3
* \|	Do not sigmap keep bits inside write_xaiger	Eddie Hung	2019-11-25	1	-1/+1
* \|	write_xaiger back to working with whole modules only	Eddie Hung	2019-11-22	1	-5/+2
* \|	Revert "write_xaiger to not use module POs but only write outputs if driven"	Eddie Hung	2019-11-22	1	-23/+11
* \|	write_xaiger to not use module POs but only write outputs if driven	Eddie Hung	2019-11-21	1	-11/+23
* \|	abc9 to support async flops $_DFF_[NP][NP][01]_	Eddie Hung	2019-11-19	1	-1/+2
* \|	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-11-19	1	-0/+3
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\| *	Fix write_aiger bug added in 524af21	Clifford Wolf	2019-11-04	1	-0/+3
* \|	Rename $currQ to $abc9_currQ	Eddie Hung	2019-10-07	1	-8/+8
* \|	Get rid of latch_* in write_xaiger	Eddie Hung	2019-10-07	1	-7/+1
* \|	Remove "write_xaiger -zinit"	Eddie Hung	2019-10-07	1	-16/+6
* \|	Add comment on default flop init	Eddie Hung	2019-10-07	1	-0/+1
* \|	Get rid of output_port lookup	Eddie Hung	2019-10-07	1	-14/+8
* \|	Do not require changes to cells_sim.v; try and work out comb model	Eddie Hung	2019-10-05	1	-48/+70
* \|	Error if $currQ not found	Eddie Hung	2019-10-05	1	-0/+4
* \|	Fix merge issues	Eddie Hung	2019-10-04	1	-1/+1
* \|	Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff	Eddie Hung	2019-10-04	1	-11/+11
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\| *	Rename abc_* names/attributes to more precisely be abc9_*	Eddie Hung	2019-10-04	1	-9/+9
* \|	No need to punch ports at all	Eddie Hung	2019-09-30	1	-0/+24
* \|	Remove need for $currQ port connection	Eddie Hung	2019-09-30	1	-3/+3