aboutsummaryrefslogtreecommitdiffstats
path: root/backends/aiger
diff options
context:
space:
mode:
authorEddie Hung <eddie@fpgeh.com>2019-12-27 11:30:18 -0800
committerEddie Hung <eddie@fpgeh.com>2019-12-27 11:30:18 -0800
commit49881b4468bbd02ac141495dd3b30c9739eb5072 (patch)
treef2f84c864870618c13c07c01591bba5fe4907688 /backends/aiger
parent509070f82fa458ccc8515eb4b09f1e4ab7068110 (diff)
downloadyosys-49881b4468bbd02ac141495dd3b30c9739eb5072.tar.gz
yosys-49881b4468bbd02ac141495dd3b30c9739eb5072.tar.bz2
yosys-49881b4468bbd02ac141495dd3b30c9739eb5072.zip
write_xaiger: fix arrival times for non boxes
Diffstat (limited to 'backends/aiger')
-rw-r--r--backends/aiger/xaiger.cc43
1 files changed, 25 insertions, 18 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 78496b13c..e03f95eaa 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -250,41 +250,48 @@ struct XAigerWriter
}
RTLIL::Module* inst_module = module->design->module(cell->type);
- if (inst_module && inst_module->attributes.count("\\abc9_box_id")) {
- abc9_box_seen = true;
-
- toposort.node(cell->name);
+ if (inst_module) {
+ bool abc9_box = inst_module->attributes.count("\\abc9_box_id");
for (const auto &conn : cell->connections()) {
auto port_wire = inst_module->wire(conn.first);
- if (port_wire->port_input) {
- // Ignore inout for the sake of topographical ordering
- if (port_wire->port_output) continue;
- for (auto bit : sigmap(conn.second))
- bit_users[bit].insert(cell->name);
- }
+ int arrival = 0;
if (port_wire->port_output) {
- int arrival = 0;
auto it = port_wire->attributes.find("\\abc9_arrival");
if (it != port_wire->attributes.end()) {
if (it->second.flags != 0)
log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type));
arrival = it->second.as_int();
}
+ }
- for (auto bit : sigmap(conn.second)) {
- bit_drivers[bit].insert(cell->name);
- if (arrival)
- arrival_times[bit] = arrival;
+ if (abc9_box) {
+ if (port_wire->port_input) {
+ // Ignore inout for the sake of topographical ordering
+ if (port_wire->port_output) continue;
+ for (auto bit : sigmap(conn.second))
+ bit_users[bit].insert(cell->name);
}
+ if (port_wire->port_output)
+ for (auto bit : sigmap(conn.second)) {
+ bit_drivers[bit].insert(cell->name);
+ if (arrival)
+ arrival_times[bit] = arrival;
+ }
}
}
- if (inst_module->attributes.count("\\abc9_flop"))
- flop_boxes.push_back(cell);
- continue;
+ if (abc9_box) {
+ abc9_box_seen = true;
+
+ toposort.node(cell->name);
+
+ if (inst_module->attributes.count("\\abc9_flop"))
+ flop_boxes.push_back(cell);
+ continue;
+ }
}
bool cell_known = inst_module || cell->known();