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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-25 15:43:37 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-25 15:43:37 -0800 |
| commit | da51492dbcc9f19a4808ef18e8ae1222bc55b118 (patch) | |
| tree | 3b89cb5495d930ff5f1a641ea9868b12e4c673cc /backends/aiger | |
| parent | 7f0914a40896b566a8b1e139438bd585a9ae2b4b (diff) | |
| download | yosys-da51492dbcc9f19a4808ef18e8ae1222bc55b118.tar.gz yosys-da51492dbcc9f19a4808ef18e8ae1222bc55b118.tar.bz2 yosys-da51492dbcc9f19a4808ef18e8ae1222bc55b118.zip | |
Fold loop
Diffstat (limited to 'backends/aiger')
| -rw-r--r-- | backends/aiger/xaiger.cc | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 763a14909..37ef30522 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -189,6 +189,7 @@ struct XAigerWriter if (bit != wirebit) alias_map[bit] = wirebit; input_bits.insert(wirebit); + undriven_bits.erase(bit); } if (wire->port_output || keep) { @@ -196,6 +197,8 @@ struct XAigerWriter if (bit != wirebit) alias_map[wirebit] = bit; output_bits.insert(wirebit); + if (!wire->port_input) + unused_bits.erase(bit); } else log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit)); @@ -203,12 +206,6 @@ struct XAigerWriter } } - for (auto bit : input_bits) - undriven_bits.erase(sigmap(bit)); - for (auto bit : output_bits) - if (!bit.wire->port_input) - unused_bits.erase(bit); - // TODO: Speed up toposort -- ultimately we care about // box ordering, but not individual AIG cells dict<SigBit, pool<IdString>> bit_drivers, bit_users; |