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* | | | | Merge pull request #849 from YosysHQ/clifford/dynportsClifford Wolf2019-03-024-1/+24
|\ \ \ \ \ | |/ / / / |/| | | | Only run derive on blackbox modules when ports have dynamic size
| * | | | Only run derive on blackbox modules when ports have dynamic sizeClifford Wolf2019-03-024-1/+24
|/ / / / | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Fix $global_clock handling vs autowireClifford Wolf2019-03-021-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge pull request #847 from YosysHQ/clifford/fix785Clifford Wolf2019-03-021-0/+35
|\ \ \ \ | | | | | | | | | | Fix $readmem[hb] for mem2reg memories, fixes #785
| * | | | Fix $readmem[hb] for mem2reg memories, fixes #785Clifford Wolf2019-03-021-0/+35
|/ / / / | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge pull request #843 from YosysHQ/clifford/mem2regconstidxClifford Wolf2019-03-022-0/+13
|\ \ \ \ | | | | | | | | | | Use mem2reg on memories that only have constant-index write ports
| * | | | Use mem2reg on memories that only have constant-index write portsClifford Wolf2019-03-012-0/+13
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | Merge pull request #845 from YosysHQ/clifford/travisnomacosClifford Wolf2019-03-021-5/+5
|\ \ \ \ \ | |_|/ / / |/| | | | Disable macOS builds in Travis
| * | | | Disable macOS builds in TravisClifford Wolf2019-03-021-5/+5
|/ / / / | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Try again for passes/pmgen/ice40_dsp_pm.h ruleLarry Doolittle2019-03-012-8/+9
| | | | | | | | | | | | | | | | Tested on both in-tree and out-of-tree builds
* | | | Minor improvements in READMEClifford Wolf2019-03-011-3/+16
|/ / / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* / / Fix "write_edif -gndvccy"Clifford Wolf2019-03-011-1/+1
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #841 from mmicko/masterClifford Wolf2019-03-011-2/+3
|\ \ | | | | | | Fix ECP5 cells_sim for iverilog
| * | Fix ECP5 cells_sim for iverilogMiodrag Milanovic2019-03-011-2/+3
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* | Improve "read" error msgClifford Wolf2019-02-281-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_modeClifford Wolf2019-02-281-2/+2
|\ \ | | | | | | ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
| * | ice40: use 2 bits for READ/WRITE MODE for SB_RAM mapElms2019-02-281-2/+2
| | | | | | | | | | | | | | | | | | EBLIF output .param will only use necessary 2 bits Signed-off-by: Elms <elms@freshred.net>
* | | Hotfix for "make test"Clifford Wolf2019-02-281-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge pull request #837 from YosysHQ/clifford/fix835Clifford Wolf2019-02-281-5/+24
|\ \ \ | | | | | | | | Fix multiple issues in wreduce FF handling, fixes #835
| * | | Fix multiple issues in wreduce FF handling, fixes #835Clifford Wolf2019-02-281-5/+24
|/ / / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge pull request #834 from YosysHQ/clifford/siminitClifford Wolf2019-02-282-3/+12
|\ \ \ | | | | | | | | Add "write_verilog -siminit"
| * | | Add "write_verilog -siminit"Clifford Wolf2019-02-282-3/+12
|/ / / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Reduce amount of trailing whitespace in code baseLarry Doolittle2019-02-289-29/+29
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* | | Fix pmgen for in-tree buildsClifford Wolf2019-02-282-8/+9
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge pull request #794 from daveshah1/ecp5improveClifford Wolf2019-02-287-12/+388
|\ \ \ | | | | | | | | ECP5 Improvements
| * | | ecp5: Compatibility with Migen AsyncResetSynchronizerDavid Shah2019-02-252-0/+20
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | | ecp5: Add DDRDLLADavid Shah2019-02-191-0/+9
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | | ecp5: Add DELAYF/DELAYG blackboxesDavid Shah2019-02-191-0/+18
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | | ecp5: Add ECLKSYNCB blackboxDavid Shah2019-02-131-1/+7
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | ecp5: Full set of IO-related blackboxesDavid Shah2019-02-121-0/+102
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | ecp5: Support for flipflop initialisationDavid Shah2019-01-223-4/+199
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | ecp5: Add LSRMODE to flipflops for PRLD supportDavid Shah2019-01-211-7/+16
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | ecp5: More blackboxesDavid Shah2019-01-211-0/+17
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | ecp5: Increase threshold for ALU mappingDavid Shah2019-01-211-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | Merge pull request #827 from ucb-bar/firrtlfixesClifford Wolf2019-02-284-11/+21
|\ \ \ \ | |_|/ / |/| | | Fix FIRRTL to Verilog process instance subfield assignment.
| * | | Fix FIRRTL to Verilog process instance subfield assignment.Jim Lawson2019-02-254-11/+21
| | | | | | | | | | | | | | | | | | | | | | | | Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module. Enable tests which were disabled due to incorrect treatment of subfields. Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)
* | | | Fix pmgen for out-of-tree buildClifford Wolf2019-02-282-4/+6
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge pull request #833 from YosysHQ/clifford/fix831Clifford Wolf2019-02-281-4/+11
|\ \ \ \ | | | | | | | | | | Fix smt2 code generation for partially initialized memory words, fixe…
| * | | | Fix smt2 code generation for partially initialized memowy words, fixes #831Clifford Wolf2019-02-281-4/+11
|/ / / / | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge pull request #832 from YosysHQ/supercoverClifford Wolf2019-02-282-0/+93
|\ \ \ \ | |_|_|/ |/| | | Add "supercover" pass
| * | | Improvements in "supercover" passClifford Wolf2019-02-271-2/+18
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add "supercover" skeletonClifford Wolf2019-02-272-0/+77
|/ / / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut moduleLarry Doolittle2019-02-261-22/+22
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* | | Clean up some whitepsace outliersLarry Doolittle2019-02-263-6/+6
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* | Minor changes ontop of 71bcc4c: Remove hierarchy warning that is redundant ↵Clifford Wolf2019-02-241-5/+1
| | | | | | | | | | | | to -check Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #812 from ucb-bar/arrayhierarchyfixesClifford Wolf2019-02-243-11/+108
|\ \ | | | | | | Define basic_cell_type() function and use it to derive the cell type …
| * | Address requested changes - don't require non-$ name.Jim Lawson2019-02-223-11/+14
| | | | | | | | | | | | | | | | | | Suppress warning if name does begin with a `$`. Fix hierachy tests so they have something to grep. Announce hierarchy test types.
| * | Fix normal (non-array) hierarchy -auto-top.Jim Lawson2019-02-193-10/+74
| | | | | | | | | | | | Add simple test.
| * | Define basic_cell_type() function and use it to derive the cell type for ↵Jim Lawson2019-02-151-10/+40
| | | | | | | | | | | | array references (instead of duplicating the code).
* | | Cleanups in ARST handling in wreduceClifford Wolf2019-02-241-10/+4
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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