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Revert "dffinit -noreinit to silently continue when init value is 1'bx"
Eddie Hung
2019-05-03
1
-12
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+4
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synth_xilinx to call dffinit with -noreinit
Eddie Hung
2019-05-02
1
-1
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+1
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dffinit -noreinit to silently continue when init value is 1'bx
Eddie Hung
2019-05-02
1
-4
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+12
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Merge pull request #963 from YosysHQ/eddie/synth_xilinx_fine
Clifford Wolf
2019-05-02
3
-34
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+30
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Back to passing all xc7srl tests!
Eddie Hung
2019-05-01
1
-5
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+4
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Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fine
Eddie Hung
2019-05-01
22
-190
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+286
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WIP
Eddie Hung
2019-04-28
1
-36
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+22
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Move neg-pol to pos-pol mapping from ff_map to cells_map.v
Eddie Hung
2019-04-28
2
-9
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+12
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Revert synth_xilinx 'fine' label more to how it used to be...
Eddie Hung
2019-04-26
1
-21
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+40
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Merge pull request #978 from ucb-bar/fmtfirrtl
Eddie Hung
2019-05-01
1
-25
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+25
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Re-indent firrtl.cc:struct memory - no functional change.
Jim Lawson
2019-05-01
1
-25
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+25
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Merge branch 'master' of github.com:YosysHQ/yosys
Eddie Hung
2019-05-01
21
-176
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+273
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Merge branch 'clifford/fix883'
Clifford Wolf
2019-05-02
1
-0
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+1
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Add missing enable_undef to "sat -tempinduct-def", fixes #883
Clifford Wolf
2019-05-02
1
-0
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+1
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Merge pull request #977 from ucb-bar/fixfirrtlmem
Clifford Wolf
2019-05-01
3
-4
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+64
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Fix #938 - Crash occurs in case when use write_firrtl command
Jim Lawson
2019-05-01
3
-4
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+64
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Fix floating point exception in qwp, fixes #923
Clifford Wolf
2019-05-01
1
-1
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+1
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Fix segfault in wreduce
Clifford Wolf
2019-04-30
1
-0
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+2
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Disabled "final loop assignment" feature
Clifford Wolf
2019-04-30
1
-0
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+2
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Merge pull request #972 from YosysHQ/clifford/fix968
Clifford Wolf
2019-04-30
1
-0
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+7
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Add final loop variable assignment when unrolling for-loops, fixes #968
Clifford Wolf
2019-04-30
1
-0
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+7
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Merge pull request #966 from YosysHQ/clifford/fix956
Clifford Wolf
2019-04-30
3
-3
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+55
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Add handling of init attributes in "opt_expr -undriven"
Clifford Wolf
2019-04-30
2
-3
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+42
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Drive dangling wires with init attr with their init value, fixes #956
Clifford Wolf
2019-04-29
1
-0
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+13
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Merge pull request #962 from YosysHQ/eddie/refactor_synth_xilinx
Clifford Wolf
2019-04-30
2
-156
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+101
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Merge branch 'master' into eddie/refactor_synth_xilinx
Clifford Wolf
2019-04-30
9
-12
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+40
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Merge pull request #973 from christian-krieg/feature/python_bindings
Clifford Wolf
2019-04-30
3
-4
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+4
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Merge branch 'master' of https://github.com/YosysHQ/yosys into feature/python...
Benedikt Tutzer
2019-04-30
88
-320
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+2797
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Cleaned up root directory
Benedikt Tutzer
2019-04-30
3
-4
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+4
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Include filename in "Executing Verilog-2005 frontend" message, fixes #959
Clifford Wolf
2019-04-30
1
-2
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+2
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Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970
Clifford Wolf
2019-04-30
1
-1
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+1
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Merge pull request #960 from YosysHQ/eddie/equiv_opt_undef
Clifford Wolf
2019-04-29
1
-3
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+16
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Add -undef option to equiv_opt, passed to equiv_induct
Eddie Hung
2019-04-26
1
-3
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+16
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Merge pull request #967 from olegendo/depfile_esc_spaces
Clifford Wolf
2019-04-29
3
-2
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+17
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fix codestyle formatting
Oleg Endo
2019-04-29
3
-14
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+14
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escape spaces with backslash when writing dep file
Oleg Endo
2019-04-29
3
-2
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+17
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Refactor synth_xilinx to auto-generate doc
Eddie Hung
2019-04-26
1
-153
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+95
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Cleanup ice40
Eddie Hung
2019-04-26
1
-4
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+6
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Copy with 1'bx padding in $shiftx
Eddie Hung
2019-04-28
1
-1
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+11
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Where did this check come from!?!
Eddie Hung
2019-04-26
1
-1
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+0
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Misspelling
Eddie Hung
2019-04-25
1
-1
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+1
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Merge pull request #957 from YosysHQ/oai4fix
Clifford Wolf
2019-04-23
2
-2
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+2
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Fixes for OAI4 cell implementation
David Shah
2019-04-23
2
-2
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+2
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Format some names using inline code
Eddie Hung
2019-04-23
1
-2
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+2
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Fix spelling
Eddie Hung
2019-04-23
1
-1
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+1
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Remove some left-over log_dump()
Clifford Wolf
2019-04-23
1
-2
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+0
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Merge pull request #914 from YosysHQ/xc7srl
Eddie Hung
2019-04-22
8
-41
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+382
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Update help message
Eddie Hung
2019-04-22
1
-1
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+1
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Move 'shregmap -tech xilinx' into map_cells
Eddie Hung
2019-04-22
1
-17
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+20
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Merge remote-tracking branch 'origin/master' into xc7srl
Eddie Hung
2019-04-22
39
-71
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+3146
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