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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-28 13:04:34 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-28 13:04:34 -0700 |
| commit | acafcdc94dc148b2bf9c8faef173e5b2b54e1ac5 (patch) | |
| tree | 4b9df8197a83c3373a3ab12956d4c5daba1b9d39 | |
| parent | ea0e0722bb42254ac8c63eb41664d9dfb7973aec (diff) | |
| download | yosys-acafcdc94dc148b2bf9c8faef173e5b2b54e1ac5.tar.gz yosys-acafcdc94dc148b2bf9c8faef173e5b2b54e1ac5.tar.bz2 yosys-acafcdc94dc148b2bf9c8faef173e5b2b54e1ac5.zip | |
Copy with 1'bx padding in $shiftx
| -rw-r--r-- | passes/techmap/shregmap.cc | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index a541b33be..75eedfbcc 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -178,7 +178,17 @@ struct ShregmapTechXilinx7 : ShregmapTech // Only map if $shiftx exclusively covers the shift register if (shiftx->type == "$shiftx") { - if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int()) + if (GetSize(taps) > shiftx->getParam("\\A_WIDTH").as_int()) + return false; + // Due to padding the most significant bits of A may be 1'bx, + // and if so, discount them + if (GetSize(taps) < shiftx->getParam("\\A_WIDTH").as_int()) { + const SigSpec A = shiftx->getPort("\\A"); + const int A_width = shiftx->getParam("\\A_WIDTH").as_int(); + for (int i = GetSize(taps); i < A_width; ++i) + if (A[i] != RTLIL::Sx) return false; + } + else if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int()) return false; } else if (shiftx->type == "$mux") { |