| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Revert "No need for $__mul anymore?" | Eddie Hung | 2019-09-25 | 1 | -8/+8 |
| | | | | | This reverts commit 1d875ac76a354f654f28b9632d83f6b43542e827. | ||||
| * | Rework xilinx_dsp postAdd for new wreduce call | Eddie Hung | 2019-09-25 | 1 | -3/+3 |
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| * | Only wreduce on t:$add | Eddie Hung | 2019-09-25 | 1 | -1/+1 |
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| * | Remove _TECHMAP_CELLTYPE_ check since all $mul | Eddie Hung | 2019-09-25 | 1 | -6/+2 |
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| * | Fix memory issue since SigSpec& could be invalidated | Eddie Hung | 2019-09-25 | 1 | -6/+10 |
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| * | No need for $__mul anymore? | Eddie Hung | 2019-09-25 | 1 | -8/+8 |
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| * | unextend only used in init | Eddie Hung | 2019-09-25 | 1 | -2/+1 |
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| * | Call 'wreduce' after mul2dsp to avoid unextend() | Eddie Hung | 2019-09-25 | 2 | -5/+5 |
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| * | Oops. Actually use __NAME__ in ABC_DSP48E1 macro | Eddie Hung | 2019-09-25 | 1 | -1/+1 |
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| * | Add (* techmap_autopurge *) to abc_unmap.v too | Eddie Hung | 2019-09-23 | 1 | -11/+11 |
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| * | "abc_padding" attr for blackbox outputs that were padded, remove them later | Eddie Hung | 2019-09-23 | 2 | -4/+22 |
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| * | Force $inout.out ports to begin with '$' to indicate internal | Eddie Hung | 2019-09-23 | 2 | -3/+3 |
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| * | Add techmap_autopurge to outputs in abc_map.v too | Eddie Hung | 2019-09-23 | 1 | -11/+11 |
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| * | Revert "Add a xilinx_finalise pass" | Eddie Hung | 2019-09-23 | 3 | -87/+0 |
| | | | | | This reverts commit 23d90e0439ffef510632ce45a3d2aff1c129f405. | ||||
| * | Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect" | Eddie Hung | 2019-09-23 | 1 | -38/+38 |
| | | | | | This reverts commit 67c2db3486a7b2ff34f89dc861fb66d51ba6101b. | ||||
| * | Revert "Vivado does not like zero width port connections" | Eddie Hung | 2019-09-23 | 1 | -2/+2 |
| | | | | | This reverts commit 895e2befa76bd326cc47fd40de112ea067fcaf98. | ||||
| * | Vivado does not like zero width port connections | Eddie Hung | 2019-09-23 | 1 | -2/+2 |
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| * | Remove (* techmap_autopurge *) from abc_unmap.v since no effect | Eddie Hung | 2019-09-23 | 1 | -38/+38 |
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| * | Add a xilinx_finalise pass | Eddie Hung | 2019-09-23 | 3 | -0/+87 |
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| * | Set [AB]CASCREG to legal values | Eddie Hung | 2019-09-23 | 1 | -6/+10 |
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| * | Comment to explain separating CREG packing | Eddie Hung | 2019-09-23 | 1 | -0/+8 |
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| * | Separate out CREG packing into new pattern, to avoid conflict with PREG | Eddie Hung | 2019-09-23 | 4 | -46/+273 |
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| * | Move log_debug("\n") later | Eddie Hung | 2019-09-23 | 1 | -1/+1 |
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| * | Move unextend initialisation later | Eddie Hung | 2019-09-23 | 1 | -12/+9 |
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| * | Use new port() overload once more | Eddie Hung | 2019-09-23 | 1 | -2/+2 |
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| * | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-23 | 2 | -1/+69 |
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| | * | Merge pull request #1392 from YosysHQ/eddie/fix1391 | Clifford Wolf | 2019-09-21 | 2 | -1/+69 |
| | |\ | | | | | | | (* techmap_autopurge *) fixes when ports aren't consistently-sized | ||||
| | | * | Hell let's add the original #1381 testcase too | Eddie Hung | 2019-09-20 | 1 | -3/+22 |
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| | | * | Revert abc9.cc | Eddie Hung | 2019-09-20 | 1 | -1/+1 |
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| | | * | Add testcase | Eddie Hung | 2019-09-20 | 1 | -0/+43 |
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| | | * | Trim mismatched connection to be same (smallest) size | Eddie Hung | 2019-09-20 | 1 | -0/+6 |
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| | | * | Fix first testcase in #1391 | Eddie Hung | 2019-09-20 | 2 | -2/+2 |
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| * | | Grammar | Eddie Hung | 2019-09-20 | 1 | -1/+1 |
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| * | | Use new port/param overload in pmg | Eddie Hung | 2019-09-20 | 4 | -22/+22 |
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| * | | Output pattern matcher items as log_debug() | Eddie Hung | 2019-09-20 | 2 | -31/+27 |
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| * | | OPMODE is port not param | Eddie Hung | 2019-09-20 | 1 | -7/+6 |
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| * | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-20 | 4 | -18/+50 |
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| | * | Merge pull request #1386 from YosysHQ/clifford/fix1360 | Clifford Wolf | 2019-09-20 | 2 | -18/+30 |
| | |\ | | | | | | | Fix handling of read_verilog config in AstModule::reprocess_module() | ||||
| | | * | Fix handling of read_verilog config in AstModule::reprocess_module(), fixes ↵ | Clifford Wolf | 2019-09-20 | 2 | -18/+30 |
| | |/ | | | | | | | | | | | #1360 Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Update CHANGELOG | Clifford Wolf | 2019-09-20 | 1 | -0/+2 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Add "add -mod" | Clifford Wolf | 2019-09-20 | 1 | -0/+18 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Merge pull request #1384 from YosysHQ/clifford/fix1381 | Clifford Wolf | 2019-09-20 | 1 | -5/+49 |
| | |\ | | | | | | | Add techmap_autopurge attribute | ||||
| * | | | Do not run xilinx_dsp_cascadeAB for now | Eddie Hung | 2019-09-20 | 1 | -1/+2 |
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| * | | | WIP for xiinx_dsp_cascadeAB | Eddie Hung | 2019-09-20 | 1 | -3/+499 |
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| * | | | Run until convergence | Eddie Hung | 2019-09-20 | 1 | -3/+9 |
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| * | | | Cleanup ice40_dsp.pmg | Eddie Hung | 2019-09-20 | 1 | -12/+6 |
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| * | | | Cleanup xilinx_dsp | Eddie Hung | 2019-09-20 | 1 | -1/+1 |
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| * | | | More exceptions | Eddie Hung | 2019-09-20 | 1 | -2/+2 |
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| * | | | Fix signedness bug | Eddie Hung | 2019-09-20 | 1 | -2/+2 |
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| * | | | Update doc | Eddie Hung | 2019-09-20 | 1 | -2/+2 |
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index : iCE40/yosys | |
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