diff options
author | Eddie Hung <eddie@fpgeh.com> | 2019-09-20 12:18:37 -0700 |
---|---|---|
committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-20 12:18:37 -0700 |
commit | eb597431f03cb402db4fc8a514c031efc29e6580 (patch) | |
tree | 480257edf8ee092ba5ec8a3b5f53ecb652363a17 | |
parent | 0bca366bcd0f936bc232cf869ef13818572664f8 (diff) | |
download | yosys-eb597431f03cb402db4fc8a514c031efc29e6580.tar.gz yosys-eb597431f03cb402db4fc8a514c031efc29e6580.tar.bz2 yosys-eb597431f03cb402db4fc8a514c031efc29e6580.zip |
Do not run xilinx_dsp_cascadeAB for now
-rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 7530eb5ad..4790cc69d 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -551,7 +551,8 @@ struct XilinxDspPass : public Pass { did_something = false; xilinx_dsp_cascade_pm pmc(module, module->selected_cells()); pmc.run_xilinx_dsp_cascadeP(); - pmc.run_xilinx_dsp_cascadeAB(); + //pmc.run_xilinx_dsp_cascadeAB(); + break; } while (did_something); } } |