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* Merge pull request #3667 from jix/xprop-test-make-fixJannis Harder2023-02-101-1/+1
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| * tests: in xprop tests, use MAKE variable if setJannis Harder2023-02-101-1/+1
* | Bump versiongithub-actions[bot]2023-02-091-1/+1
* | Next dev cycleMiodrag Milanovic2023-02-082-2/+5
* | Release version 0.26Miodrag Milanovic2023-02-082-4/+4
* | Merge pull request #3662 from YosysHQ/micko/wide_case_select_boxJannis Harder2023-02-082-4/+82
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| * For case select values use Sa instead of Sx and SzMiodrag Milanovic2023-02-082-5/+42
| * Add verific import support for OPER_WIDE_CASE_SELECT_BOXMiodrag Milanovic2023-02-061-0/+41
* | Updated changelogMiodrag Milanovic2023-02-082-0/+21
* | Merge pull request #3625 from povik/show_cleanupN. Engelhardt2023-02-061-56/+82
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| * | passes: show: s/pos/bitpos/ for readabilityMartin Povišer2023-01-131-4/+5
| * | passes: show: Reuse string parts in generation of portboxesMartin Povišer2023-01-131-2/+5
| * | passes: show: Touch chunk iteration in gen_portboxMartin Povišer2023-01-131-8/+11
| * | passes: show: Label no_signode flagMartin Povišer2023-01-131-20/+19
| * | passes: show: Simplify wire bit range logicMartin Povišer2023-01-131-8/+10
| * | passes: show: Factor out 'join_label_pieces'Martin Povišer2023-01-131-20/+35
| * | passes: show: Label signed_suffix flagMartin Povišer2023-01-131-3/+6
| * | passes: show: s/idx/dot_idx/ for readabilityMartin Povišer2023-01-131-7/+7
| * | passes: show: Fix portbox bit ranges in case of driven signalsMartin Povišer2023-01-131-1/+1
* | | Bump versiongithub-actions[bot]2023-02-051-1/+1
* | | Merge pull request #3659 from whitequark/update-abcCatherine2023-02-041-1/+1
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| * | | Bump ABCREV to fix WASM build.Catherine2023-02-041-1/+1
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* | | Bump versiongithub-actions[bot]2023-02-041-1/+1
* | | backends/firrtl: Ensure `modInstance` is validAki Van Ness2023-02-031-0/+6
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* | Bump versiongithub-actions[bot]2023-02-021-1/+1
* | Merge pull request #3655 from jix/smt2_fix_b_op_widthJannis Harder2023-02-011-1/+4
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| * | smt2: Fix operation width computation for boolean producing cellsJannis Harder2023-02-011-1/+4
* | | Bump versiongithub-actions[bot]2023-01-311-1/+1
* | | Merge pull request #3650 from jix/rtlil_roundtrip_z_bitsJannis Harder2023-01-304-1/+22
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| * | | backends/rtlil: Do not shorten a value with z bits to 'xJannis Harder2023-01-294-1/+22
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* | | add option to fsm_detect to ignore self-resettingN. Engelhardt2023-01-301-7/+22
* | | add pmux option to bmuxmap for better fsm detection with verific frontendN. Engelhardt2023-01-302-6/+75
* | | Bump versiongithub-actions[bot]2023-01-301-1/+1
* | | Resolve struct member package typesDag Lem2023-01-292-0/+11
* | | Handle struct members of union type (#3641)Dag Lem2023-01-293-2/+18
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* | Bump versiongithub-actions[bot]2023-01-261-1/+1
* | Merge pull request #3647 from jix/formalff-hierarchy-fixMiodrag Milanović2023-01-251-1/+1
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| * | formalff: Fix crash with _NOT_ gates in -hierarchy modeJannis Harder2023-01-251-1/+1
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* | Bump versiongithub-actions[bot]2023-01-241-1/+1
* | Merge pull request #3624 from jix/sim_ywMiodrag Milanović2023-01-2315-113/+1722
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| * | sim/formalff: Clock handling for yw cosimJannis Harder2023-01-115-33/+274
| * | sim: Improvements and fixes for yw cosimJannis Harder2023-01-116-52/+154
| * | Support for BTOR witness to Yosys witness conversionJannis Harder2023-01-115-20/+312
| * | aiger: Use new JSON code for writing aiger witness map filesJannis Harder2023-01-113-55/+96
| * | Add json.{h,cc} for pretty printing JSONJannis Harder2023-01-113-1/+223
| * | sim: New -append option for Yosys witness cosimJannis Harder2023-01-111-5/+14
| * | sim: Add Yosys witness (.yw) cosimulationJannis Harder2023-01-111-3/+194
| * | New kernel/yw.{h,cc} to support reading Yosys witness filesJannis Harder2023-01-113-1/+380
| * | sim: Only check formal cells during gclk simulation updatesJannis Harder2023-01-111-16/+19
| * | sim: Internal API to set $initstateJannis Harder2023-01-111-0/+11
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