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| author | Miodrag Milanovic <mmicko@gmail.com> | 2023-02-08 09:22:48 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2023-02-08 09:22:48 +0100 |
| commit | 109b88c3791c87e819fb5a6c3c52f964655fd379 (patch) | |
| tree | c2a53e73a48dadb701c73ab0e97cbb515a64ee33 | |
| parent | e7e37df91b6e24ff76009179e568de33ad317a00 (diff) | |
| download | yosys-109b88c3791c87e819fb5a6c3c52f964655fd379.tar.gz yosys-109b88c3791c87e819fb5a6c3c52f964655fd379.tar.bz2 yosys-109b88c3791c87e819fb5a6c3c52f964655fd379.zip | |
For case select values use Sa instead of Sx and Sz
| -rw-r--r-- | frontends/verific/verific.cc | 46 | ||||
| -rw-r--r-- | frontends/verific/verific.h | 1 |
2 files changed, 42 insertions, 5 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 92a2a5ce1..c1e9fc7d0 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -361,10 +361,16 @@ RTLIL::SigSpec VerificImporter::operatorInport(Instance *inst, const char *portn for (unsigned i = 0; i < portbus->Size(); i++) { Net *net = inst->GetNet(portbus->ElementAtIndex(i)); if (net) { - if (net->IsGnd()) - sig.append(RTLIL::State::S0); - else if (net->IsPwr()) - sig.append(RTLIL::State::S1); + if (net->IsConstant()) { + if (net->IsGnd()) + sig.append(RTLIL::State::S0); + else if (net->IsPwr()) + sig.append(RTLIL::State::S1); + else if (net->IsX()) + sig.append(RTLIL::State::Sx); + else + sig.append(RTLIL::State::Sz); + } else sig.append(net_map_at(net)); } else @@ -379,6 +385,36 @@ RTLIL::SigSpec VerificImporter::operatorInport(Instance *inst, const char *portn } } +RTLIL::SigSpec VerificImporter::operatorInportCase(Instance *inst, const char *portname) +{ + PortBus *portbus = inst->View()->GetPortBus(portname); + if (portbus) { + RTLIL::SigSpec sig; + for (unsigned i = 0; i < portbus->Size(); i++) { + Net *net = inst->GetNet(portbus->ElementAtIndex(i)); + if (net) { + if (net->IsConstant()) { + if (net->IsGnd()) + sig.append(RTLIL::State::S0); + else if (net->IsPwr()) + sig.append(RTLIL::State::S1); + else + sig.append(RTLIL::State::Sa); + } + else + sig.append(net_map_at(net)); + } else + sig.append(RTLIL::State::Sa); + } + return sig; + } else { + Port *port = inst->View()->GetPort(portname); + log_assert(port != NULL); + Net *net = inst->GetNet(port); + return net_map_at(net); + } +} + RTLIL::SigSpec VerificImporter::operatorOutput(Instance *inst, const pool<Net*, hash_ptr_ops> *any_all_nets) { RTLIL::SigSpec sig; @@ -993,7 +1029,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr { RTLIL::SigSpec sig_out_val = operatorInport(inst, "out_value"); RTLIL::SigSpec sig_select = operatorInport(inst, "select"); - RTLIL::SigSpec sig_select_values = operatorInport(inst, "select_values"); + RTLIL::SigSpec sig_select_values = operatorInportCase(inst, "select_values"); RTLIL::SigSpec sig_data_values = operatorInport(inst, "data_values"); RTLIL::SigSpec sig_data_default = operatorInport(inst, "default_value"); diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h index d9f0077db..44485751c 100644 --- a/frontends/verific/verific.h +++ b/frontends/verific/verific.h @@ -87,6 +87,7 @@ struct VerificImporter RTLIL::SigSpec operatorInput1(Verific::Instance *inst); RTLIL::SigSpec operatorInput2(Verific::Instance *inst); RTLIL::SigSpec operatorInport(Verific::Instance *inst, const char *portname); + RTLIL::SigSpec operatorInportCase(Verific::Instance *inst, const char *portname); RTLIL::SigSpec operatorOutput(Verific::Instance *inst, const pool<Verific::Net*, hash_ptr_ops> *any_all_nets = nullptr); bool import_netlist_instance_gates(Verific::Instance *inst, RTLIL::IdString inst_name); |