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* Merge pull request #3681 from keszocze/keszocze-patch-dsp48e1-init-dregN. Engelhardt2023-02-171-1/+1
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| * Check DREG attributeOliver Keszöcze2023-02-171-1/+1
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* Bump versiongithub-actions[bot]2023-02-171-1/+1
* fabulous: Add CLK to BRAM interface primitivesgatecat2023-02-161-3/+3
* Bump versiongithub-actions[bot]2023-02-161-1/+1
* Merge pull request #3672 from jix/yw-cosim-hierarchy-fixesJannis Harder2023-02-151-1/+25
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| * sim: For yw cosim, drive parent module's signals for input portsJannis Harder2023-02-131-1/+25
* | Merge pull request #3675 from daglem/struct-item-queriesJannis Harder2023-02-152-12/+161
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| * | Corrected tests for data and array queries on struct/union item expressionsDag Lem2023-02-151-80/+85
| * | Support for data and array queries on struct/union item expressionsDag Lem2023-02-152-12/+156
* | | Merge pull request #3671 from zachjs/masterJannis Harder2023-02-152-0/+16
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| * | Add test for typenames using constants shadowed later onZachary Snow2023-02-122-0/+16
* | | Merge pull request #3661 from daglem/struct-array-range-offsetJannis Harder2023-02-152-22/+51
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| * | | Handle range offsets in packed arrays within packed structsDag Lem2023-02-052-22/+51
* | | | Bump versiongithub-actions[bot]2023-02-151-1/+1
* | | | Merge pull request #2995 from georgerennie/cover_precondJannis Harder2023-02-142-0/+44
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| * | | | chformal: Note about using -coverenable with the Verific frontendJannis Harder2023-02-141-0/+5
| * | | | chformal: Rename -coverprecond to -coverenableGeorge Rennie2022-06-182-7/+7
| * | | | chformal: Test -coverprecond and reuse the src attributeJannis Harder2022-06-182-2/+27
| * | | | chformal: Add -coverprecond optionGeorge Rennie2022-06-181-0/+14
* | | | | Merge pull request #3126 from georgerennie/equiv_make_assertionsJannis Harder2023-02-142-27/+97
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| * | | | | equiv_make: Add -make_assert optionGeorge Rennie2022-06-242-27/+97
* | | | | | gatemate: Update CC_PLL parametersPatrick Urban2023-02-141-0/+3
* | | | | | gatemate: Add CC_USR_RSTN primitivePatrick Urban2023-02-141-0/+6
* | | | | | gatemate: Ensure compatibility of LVDS ports with VHDLPatrick Urban2023-02-141-12/+12
* | | | | | Bump versiongithub-actions[bot]2023-02-141-1/+1
* | | | | | Merge pull request #3669 from jix/fix-xprop-tests-yosys-callJannis Harder2023-02-133-52/+60
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| * | | | | | xprop tests: Make iverilog invocation more portableJannis Harder2023-02-131-3/+3
| * | | | | | xprop: Test fixes and abort on test failureJannis Harder2023-02-132-3/+3
| * | | | | | xprop: Smaller subset of tests to run by defaultJannis Harder2023-02-131-44/+53
| * | | | | | verilog_backend: Do not run bwmuxmap even if in expr modeJannis Harder2023-02-131-1/+0
| * | | | | | tests: Fix path of yosys invocation in xprop testsJannis Harder2023-02-101-1/+1
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* | | | | | Bump versiongithub-actions[bot]2023-02-131-1/+1
* | | | | | Resolve package types in interfaces (#3658)Dag Lem2023-02-124-3/+34
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* | | | | Bump versiongithub-actions[bot]2023-02-111-1/+1
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* | | | Merge pull request #3667 from jix/xprop-test-make-fixJannis Harder2023-02-101-1/+1
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| * | | | tests: in xprop tests, use MAKE variable if setJannis Harder2023-02-101-1/+1
* | | | | Bump versiongithub-actions[bot]2023-02-091-1/+1
* | | | | Next dev cycleMiodrag Milanovic2023-02-082-2/+5
* | | | | Release version 0.26Miodrag Milanovic2023-02-082-4/+4
* | | | | Merge pull request #3662 from YosysHQ/micko/wide_case_select_boxJannis Harder2023-02-082-4/+82
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| * | | | For case select values use Sa instead of Sx and SzMiodrag Milanovic2023-02-082-5/+42
| * | | | Add verific import support for OPER_WIDE_CASE_SELECT_BOXMiodrag Milanovic2023-02-061-0/+41
* | | | | Updated changelogMiodrag Milanovic2023-02-082-0/+21
* | | | | Merge pull request #3625 from povik/show_cleanupN. Engelhardt2023-02-061-56/+82
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| * | | | | passes: show: s/pos/bitpos/ for readabilityMartin Povišer2023-01-131-4/+5
| * | | | | passes: show: Reuse string parts in generation of portboxesMartin Povišer2023-01-131-2/+5
| * | | | | passes: show: Touch chunk iteration in gen_portboxMartin Povišer2023-01-131-8/+11
| * | | | | passes: show: Label no_signode flagMartin Povišer2023-01-131-20/+19
| * | | | | passes: show: Simplify wire bit range logicMartin Povišer2023-01-131-8/+10
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