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* Remove unnecessary common.v(assertions for testbenches).SergeyDegtyar2019-08-301-47/+0
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* Remove simulation from run-test.sh (unnecessary paths)SergeyDegtyar2019-08-301-16/+9
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* Remove simulation from run-test.shSergeyDegtyar2019-08-301-6/+0
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* Merge pull request #2 from YosysHQ/masterSergey2019-08-2910-127/+341
|\ | | | | Pull from upstream
| * Fix typo that's gone unnoticed for 5 months!?!Eddie Hung2019-08-291-1/+1
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| * Bump YOSYS_VERClifford Wolf2019-08-291-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #1334 from YosysHQ/clifford/async2synclatchEddie Hung2019-08-281-1/+36
| |\ | | | | | | Add $dlatch support to async2sync
| * | Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendorEddie Hung2019-08-281-3/+8
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| * | Merge pull request #1332 from YosysHQ/dave/ecp5gsrDavid Shah2019-08-286-54/+212
| |\ \ | | | | | | | | ecp5: Add GSR and SGSR support
| | * | ecp5: Add GSR supportDavid Shah2019-08-276-54/+212
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | Merge pull request #1335 from YosysHQ/clifford/paramapClifford Wolf2019-08-281-68/+119
| |\ \ \ | | | | | | | | | | Add "paramap" pass
| | * | | Fix typoClifford Wolf2019-08-281-2/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | Add "paramap" passClifford Wolf2019-08-281-67/+118
| |/ / / | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge pull request #3 from YosysHQ/Sergey/tests_ice40Sergey2019-08-2974-820/+3636
|\ \ \ \ | | | | | | | | | | Merge my changes to tests_ice40 branch
| * | | | Comment out *.sh used for testbenches as we have no moreEddie Hung2019-08-281-8/+8
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| * | | | Use equiv for memory and dpramEddie Hung2019-08-284-168/+2
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| * | | | Use equiv_opt for latchesEddie Hung2019-08-282-58/+10
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| * | | | Merge remote-tracking branch 'origin/clifford/async2synclatch' into ↵Eddie Hung2019-08-2867-586/+3616
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| | * | | Add $dlatch support to async2syncClifford Wolf2019-08-281-1/+36
| | |/ / | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Merge pull request #1325 from YosysHQ/eddie/sat_initClifford Wolf2019-08-282-2/+8
| | |\ \ | | | | | | | | | | In sat: 'x' in init attr should be ignored
| | | * | Ignore all 1'bx in (* init *)Eddie Hung2019-08-271-3/+1
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| | | * | Revert to using cleanEddie Hung2019-08-271-1/+1
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| | | * | Wire with init on FF part, 1'bx on non-FF partEddie Hung2019-08-241-1/+3
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| | | * | Blocking assignmentEddie Hung2019-08-231-1/+1
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| | | * | In sat: 'x' in init attr should not override constantEddie Hung2019-08-223-1/+7
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| | * | | xilinx: Add SRLC16E primitive.Marcin Kościelnicki2019-08-271-1/+21
| | | | | | | | | | | | | | | | | | | | Fixes #1331.
| | * | | Merge pull request #1292 from YosysHQ/mwk/xilinx_bufgmapEddie Hung2019-08-2716-223/+1075
| | |\ \ \ | | | |_|/ | | |/| | Add clock buffer insertion pass, improve iopadmap.
| | | * | improve clkbuf_inhibit propagation upwards through hierarchyMarcin Kościelnicki2019-08-272-6/+45
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| | | * | Improve tests to check that clkbuf is connected to expectedEddie Hung2019-08-261-6/+21
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| | | * | Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-268-60/+405
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| | | * \ \ Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-231-1/+1
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| | | * \ \ \ Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-233-18/+36
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| | | * | | | | Check clkbuf_inhibit=1 is ignored for custom selectionEddie Hung2019-08-231-0/+1
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| | | * | | | | clkbufmap to only check clkbuf_inhibit if no selection givenEddie Hung2019-08-231-5/+18
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| | | * | | | | Add simple clkbufmap testsEddie Hung2019-08-231-0/+52
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| | | * | | | | tests/techmap/run-test.sh to cope with *.ysEddie Hung2019-08-232-7/+18
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| | | * | | | | Mention clkbuf_inhibit can be overriddenEddie Hung2019-08-231-7/+8
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| | | * | | | | Review comment from @cliffordwolfEddie Hung2019-08-231-1/+2
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| | | * | | | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-23146-1486/+4373
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| | | * \ \ \ \ \ Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-1657-3403/+3432
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| | | * | | | | | | README updatesMarcin Kościelnicki2019-08-131-0/+14
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| | | * | | | | | | move attributes to wiresMarcin Kościelnicki2019-08-138-311/+546
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| | | * | | | | | | minor review fixesMarcin Kościelnicki2019-08-132-3/+5
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| | | * | | | | | | review fixesMarcin Kościelnicki2019-08-134-47/+34
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| | | * | | | | | | Add clock buffer insertion pass, improve iopadmap.Marcin Kościelnicki2019-08-1310-93/+577
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it.
| | * | | | | | | | Add "make bumpversion"Clifford Wolf2019-08-272-0/+4
| | | |_|_|_|_|/ / | | |/| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | | | | Remove dupe in CHANGELOG, missing end quoteEddie Hung2019-08-261-2/+1
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| | * | | | | | | Merge tag 'yosys-0.9'Clifford Wolf2019-08-262-11/+107
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| | | * | | | | | | Yosys 0.9Clifford Wolf2019-08-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | | * | | | | | | Revert earliest to gcc-4.8, compile iverilog with default compilerEddie Hung2019-08-232-3/+3
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