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opt_lut: collect and display statistics.
whitequark
2018-12-05
1
-4
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+33
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opt_lut: refactor to use a worker. NFC.
whitequark
2018-12-05
1
-170
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+177
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synth_ice40: add -relut option, to run ice40_unlut and opt_lut.
whitequark
2018-12-05
1
-1
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+13
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opt_lut: new pass, to combine LUTs for tighter packing.
whitequark
2018-12-05
8
-1
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+320
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Merge pull request #716 from whitequark/ice40_unlut
Clifford Wolf
2018-12-05
3
-13
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+109
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Extract ice40_unlut pass from ice40_opt.
whitequark
2018-12-05
3
-13
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+109
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Merge pull request #719 from YosysHQ/q3k/flailing-around-trying-to-fix-osx
Serge Bazanski
2018-12-05
2
-3
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+2
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travis/osx: fix, use clang instead of gcc
Sergiusz Bazanski
2018-12-05
2
-3
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+2
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Fix typo
Clifford Wolf
2018-12-04
1
-1
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+1
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Merge pull request #702 from smunaut/min_ce_use
Clifford Wolf
2018-12-04
2
-1
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+50
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ice40: Add option to only use CE if it'd be use by more than X FFs
Sylvain Munaut
2018-11-27
1
-0
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+14
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dff2dffe: Add option for unmap to only remove DFFE with low CE signal use
Sylvain Munaut
2018-11-27
1
-1
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+36
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Merge pull request #676 from rafaeltp/master
Clifford Wolf
2018-12-01
1
-10
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+17
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using [i] to access individual bits of SigSpec and merging bits into a tmp Si...
rafaeltp
2018-10-21
1
-11
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+12
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cleaning up for PR
rafaeltp
2018-10-20
2
-6
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+2
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fixing code style
rafaeltp
2018-10-20
1
-1
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+1
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solves #675
rafaeltp
2018-10-20
2
-11
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+21
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Merge pull request #1 from YosysHQ/master
rafaeltp
2018-10-20
20
-89
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+869
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Improve ConstEval error handling for non-eval cell types
Clifford Wolf
2018-11-29
2
-9
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+19
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Add iteration limit to "opt_muxtree"
Clifford Wolf
2018-11-20
1
-1
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+17
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Update ABC to git rev 2ddc57d
Clifford Wolf
2018-11-13
1
-1
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+1
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Add "write_aiger -I -O -B"
Clifford Wolf
2018-11-12
1
-2
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+36
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Merge branch 'master' of github.com:YosysHQ/yosys
Clifford Wolf
2018-11-12
4
-1
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+1044
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Merge pull request #697 from eddiehung/xilinx_ps7
Clifford Wolf
2018-11-12
2
-0
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+624
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Add support for Xilinx PS7 block
Eddie Hung
2018-11-10
2
-0
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+624
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Merge pull request #695 from daveshah1/ecp5_bb
Clifford Wolf
2018-11-12
2
-1
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+420
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ecp5: Add 'fake' DCU parameters
David Shah
2018-11-09
1
-0
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+11
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ecp5: Add blackboxes for ancillary DCU cells
David Shah
2018-11-09
1
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+18
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ecp5: Adding some blackbox cells
David Shah
2018-11-07
2
-1
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+391
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Update ABC to git rev 68da3cf
Clifford Wolf
2018-11-11
1
-1
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+1
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Set Verific flag vhdl_support_variable_slice=1
Clifford Wolf
2018-11-09
1
-0
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+1
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Merge pull request #696 from arjenroodselaar/verific_darwin
Clifford Wolf
2018-11-09
1
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+4
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Use appropriate static libraries when building with Verific on MacOS
Arjen Roodselaar
2018-11-07
1
-0
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+4
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Fix "make ystests" to use correct Yosys binary
Clifford Wolf
2018-11-08
1
-1
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+1
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Merge pull request #693 from YosysHQ/rlimit
Clifford Wolf
2018-11-07
1
-8
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+11
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Limit stack size to 16 MB on Darwin
Clifford Wolf
2018-11-07
1
-1
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+4
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Fix for improved smtio.py rlimit code
Clifford Wolf
2018-11-06
1
-1
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+1
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Improve stack rlimit code in smtio.py
Clifford Wolf
2018-11-06
1
-8
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+8
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Merge pull request #694 from trcwm/dffmap_expr_fix
Clifford Wolf
2018-11-06
1
-1
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+10
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DFFLIBMAP: changed 'missing pin' error into a warning with additional reason/...
Niels Moseley
2018-11-06
1
-1
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+10
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Run solver in non-incremental mode whem smtio.py is configured for non-increm...
Clifford Wolf
2018-11-06
1
-3
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+12
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Update ABC rev to 4d56acf
Clifford Wolf
2018-11-06
1
-1
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+1
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Allow square brackets in liberty identifiers
Clifford Wolf
2018-11-05
2
-3
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+4
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Merge pull request #691 from arjenroodselaar/stacksize
Clifford Wolf
2018-11-05
1
-1
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+6
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Use conservative stack size for SMT2 on MacOS
Arjen Roodselaar
2018-11-04
1
-1
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+6
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Add warning for SV "restrict" without "property"
Clifford Wolf
2018-11-04
1
-2
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+11
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Add proper error message for when smtbmc "append" fails
Clifford Wolf
2018-11-04
1
-2
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+10
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Various indenting fixes in AST front-end (mostly space vs tab issues)
Clifford Wolf
2018-11-04
3
-99
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+69
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Merge pull request #687 from trcwm/master
Clifford Wolf
2018-11-04
2
-4
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+10
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Liberty file newline handling is more relaxed. More descriptive error message
Niels Moseley
2018-11-03
1
-4
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+7
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