| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | If init is 1'bx, do not add to dict as per @cliffordwolf | Eddie Hung | 2019-05-03 | 1 | -1/+2 |
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| * | Revert "dffinit -noreinit to silently continue when init value is 1'bx" | Eddie Hung | 2019-05-03 | 1 | -12/+4 |
| | | | | | This reverts commit aa081f83c791b1d666214776aaf744a80ce6a690. | ||||
| * | synth_xilinx to call dffinit with -noreinit | Eddie Hung | 2019-05-02 | 1 | -1/+1 |
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| * | dffinit -noreinit to silently continue when init value is 1'bx | Eddie Hung | 2019-05-02 | 1 | -4/+12 |
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| * | Merge pull request #963 from YosysHQ/eddie/synth_xilinx_fine | Clifford Wolf | 2019-05-02 | 3 | -34/+30 |
| |\ | | | | | Revert synth_xilinx 'fine' label more to how it used to be... | ||||
| | * | Back to passing all xc7srl tests! | Eddie Hung | 2019-05-01 | 1 | -5/+4 |
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| | * | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fine | Eddie Hung | 2019-05-01 | 22 | -190/+286 |
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| | * | | WIP | Eddie Hung | 2019-04-28 | 1 | -36/+22 |
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| | * | | Move neg-pol to pos-pol mapping from ff_map to cells_map.v | Eddie Hung | 2019-04-28 | 2 | -9/+12 |
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| | * | | Revert synth_xilinx 'fine' label more to how it used to be... | Eddie Hung | 2019-04-26 | 1 | -21/+40 |
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| * | | | Merge pull request #978 from ucb-bar/fmtfirrtl | Eddie Hung | 2019-05-01 | 1 | -25/+25 |
| |\ \ \ | |_|/ |/| | | Re-indent firrtl.cc:struct memory - no functional change. | ||||
| | * | | Re-indent firrtl.cc:struct memory - no functional change. | Jim Lawson | 2019-05-01 | 1 | -25/+25 |
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| * | | | Merge branch 'master' of github.com:YosysHQ/yosys | Eddie Hung | 2019-05-01 | 21 | -176/+273 |
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| | * | | Merge branch 'clifford/fix883' | Clifford Wolf | 2019-05-02 | 1 | -0/+1 |
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| | | * | | Add missing enable_undef to "sat -tempinduct-def", fixes #883 | Clifford Wolf | 2019-05-02 | 1 | -0/+1 |
| | |/ / | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Merge pull request #977 from ucb-bar/fixfirrtlmem | Clifford Wolf | 2019-05-01 | 3 | -4/+64 |
| | |\ \ | | | | | | | | | Fix #938 - Crash occurs in case when use write_firrtl command | ||||
| | | * | | Fix #938 - Crash occurs in case when use write_firrtl command | Jim Lawson | 2019-05-01 | 3 | -4/+64 |
| | | | | | | | | | | | | | | | | | | | | | | | | | Add missing memory initialization. Sanity-check memory parameters. Add Cell pointer to memory object (for error reporting). | ||||
| | * | | | Fix floating point exception in qwp, fixes #923 | Clifford Wolf | 2019-05-01 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | Fix segfault in wreduce | Clifford Wolf | 2019-04-30 | 1 | -0/+2 |
| | |/ / | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Disabled "final loop assignment" feature | Clifford Wolf | 2019-04-30 | 1 | -0/+2 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Merge pull request #972 from YosysHQ/clifford/fix968 | Clifford Wolf | 2019-04-30 | 1 | -0/+7 |
| | |\ \ | | | | | | | | | Add final loop variable assignment when unrolling for-loops | ||||
| | | * | | Add final loop variable assignment when unrolling for-loops, fixes #968 | Clifford Wolf | 2019-04-30 | 1 | -0/+7 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | Merge pull request #966 from YosysHQ/clifford/fix956 | Clifford Wolf | 2019-04-30 | 3 | -3/+55 |
| | |\ \ \ | | | | | | | | | | | Drive dangling wires with init attr with their init value | ||||
| | | * | | | Add handling of init attributes in "opt_expr -undriven" | Clifford Wolf | 2019-04-30 | 2 | -3/+42 |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | | * | | | Drive dangling wires with init attr with their init value, fixes #956 | Clifford Wolf | 2019-04-29 | 1 | -0/+13 |
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| | * | | | | Merge pull request #962 from YosysHQ/eddie/refactor_synth_xilinx | Clifford Wolf | 2019-04-30 | 2 | -156/+101 |
| | |\ \ \ \ | | | | | | | | | | | | | Refactor synth_xilinx to auto-generate doc | ||||
| | | * \ \ \ | Merge branch 'master' into eddie/refactor_synth_xilinx | Clifford Wolf | 2019-04-30 | 9 | -12/+40 |
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| | * | | | | | Merge pull request #973 from christian-krieg/feature/python_bindings | Clifford Wolf | 2019-04-30 | 3 | -4/+4 |
| | |\ \ \ \ \ | | | | | | | | | | | | | | | Feature/python bindings cleanup | ||||
| | | * \ \ \ \ | Merge branch 'master' of https://github.com/YosysHQ/yosys into ↵ | Benedikt Tutzer | 2019-04-30 | 88 | -320/+2797 |
| | | |\ \ \ \ \ | | | | |_|/ / | | | |/| | | | | | | | | | | feature/python_bindings | ||||
| | | * | | | | | Cleaned up root directory | Benedikt Tutzer | 2019-04-30 | 3 | -4/+4 |
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| | * | | | | | | Include filename in "Executing Verilog-2005 frontend" message, fixes #959 | Clifford Wolf | 2019-04-30 | 1 | -2/+2 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | | | | Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970 | Clifford Wolf | 2019-04-30 | 1 | -1/+1 |
| | | |/ / / / | |/| | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | | | Merge pull request #960 from YosysHQ/eddie/equiv_opt_undef | Clifford Wolf | 2019-04-29 | 1 | -3/+16 |
| | |\ \ \ \ \ | | | | | | | | | | | | | | | Add -undef option to equiv_opt, passed to equiv_induct | ||||
| | | * | | | | | Add -undef option to equiv_opt, passed to equiv_induct | Eddie Hung | 2019-04-26 | 1 | -3/+16 |
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| | * | | | | | Merge pull request #967 from olegendo/depfile_esc_spaces | Clifford Wolf | 2019-04-29 | 3 | -2/+17 |
| | |\ \ \ \ \ | | |_|_|_|/ | |/| | | | | escape spaces with backslash when writing dep file | ||||
| | | * | | | | fix codestyle formatting | Oleg Endo | 2019-04-29 | 3 | -14/+14 |
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| | | * | | | | escape spaces with backslash when writing dep file | Oleg Endo | 2019-04-29 | 3 | -2/+17 |
| | |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | filenames are sparated by spaces in the dep file. if a filename in the dep file contains spaces they must be escaped, otherwise the tool that reads the dep file will see multiple wrong filenames. | ||||
| | | | | * | Refactor synth_xilinx to auto-generate doc | Eddie Hung | 2019-04-26 | 1 | -153/+95 |
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| | | | | * | Cleanup ice40 | Eddie Hung | 2019-04-26 | 1 | -4/+6 |
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| * | / | | Copy with 1'bx padding in $shiftx | Eddie Hung | 2019-04-28 | 1 | -1/+11 |
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| * / / | Where did this check come from!?! | Eddie Hung | 2019-04-26 | 1 | -1/+0 |
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| * | | Misspelling | Eddie Hung | 2019-04-25 | 1 | -1/+1 |
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| * | | Merge pull request #957 from YosysHQ/oai4fix | Clifford Wolf | 2019-04-23 | 2 | -2/+2 |
| |\ \ | | | | | | | Fixes for OAI4 cell implementation | ||||
| | * | | Fixes for OAI4 cell implementation | David Shah | 2019-04-23 | 2 | -2/+2 |
| | | | | | | | | | | | | | | | | | | | Fixes #955 and the underlying issue in #954 Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | | Format some names using inline code | Eddie Hung | 2019-04-23 | 1 | -2/+2 |
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| * | | | Fix spelling | Eddie Hung | 2019-04-23 | 1 | -1/+1 |
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| * | | | Remove some left-over log_dump() | Clifford Wolf | 2019-04-23 | 1 | -2/+0 |
| |/ / | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Merge pull request #914 from YosysHQ/xc7srl | Eddie Hung | 2019-04-22 | 8 | -41/+382 |
| |\ \ | | | | | | | synth_xilinx to now infer SRL16E/SRLC32E | ||||
| | * | | Update help message | Eddie Hung | 2019-04-22 | 1 | -1/+1 |
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| | * | | Move 'shregmap -tech xilinx' into map_cells | Eddie Hung | 2019-04-22 | 1 | -17/+20 |
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