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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-03 08:06:16 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-03 08:06:16 -0700 |
| commit | e08df0c7390e1e7736c3d5b0abbe2679bf9b4518 (patch) | |
| tree | bbbcf14a457fded51a584780541c93dd888cc835 | |
| parent | fc349de0338db3831e7156a5dc60f028382bcab1 (diff) | |
| download | yosys-e08df0c7390e1e7736c3d5b0abbe2679bf9b4518.tar.gz yosys-e08df0c7390e1e7736c3d5b0abbe2679bf9b4518.tar.bz2 yosys-e08df0c7390e1e7736c3d5b0abbe2679bf9b4518.zip | |
If init is 1'bx, do not add to dict as per @cliffordwolf
| -rw-r--r-- | passes/techmap/dffinit.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc index 48390488e..0ad33dc0e 100644 --- a/passes/techmap/dffinit.cc +++ b/passes/techmap/dffinit.cc @@ -102,7 +102,8 @@ struct DffinitPass : public Pass { if (wire->attributes.count("\\init")) { Const value = wire->attributes.at("\\init"); for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) - init_bits[sigmap(SigBit(wire, i))] = value[i]; + if (value[i] != State::Sx) + init_bits[sigmap(SigBit(wire, i))] = value[i]; } if (wire->port_output) for (auto bit : sigmap(wire)) |