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* Bugfix in smt2 back-end for pure checker modulesClifford Wolf2016-11-281-0/+4
* Added support for macros as include file namesClifford Wolf2016-11-281-0/+2
* Bugfix in "read_verilog -D NAME=VAL" handlingClifford Wolf2016-11-281-3/+3
* Removed shebang line from smtio.py, fixes #279Clifford Wolf2016-11-271-1/+0
* Added wire start_offset and upto handling BLIF back-endClifford Wolf2016-11-231-1/+1
* Added wire start_offset and upto handling to splitnets cmdClifford Wolf2016-11-231-2/+8
* Merge pull request #274 from oldtopman/lcursesClifford Wolf2016-11-221-0/+5
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| * Added optional flag for linking curses with readline.oldtopman2016-11-211-0/+5
* | Added "yosys-smtbmc --append"Clifford Wolf2016-11-221-2/+20
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* Merge pull request #272 from AlexDaniel/masterClifford Wolf2016-11-191-63/+64
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| * Keep lines under 80 charactersAleks-Daniel Jakimenko-Aleksejev2016-11-191-10/+11
| * Markdownify README even furtherAleks-Daniel Jakimenko-Aleksejev2016-11-191-60/+60
* | Improved ABC default scriptsClifford Wolf2016-11-191-17/+34
* | Merge pull request #271 from azidar/bugfix-assign-wmaskClifford Wolf2016-11-191-0/+1
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| * Bugfix: include assign to write-maskAdam Izraelevitz2016-11-181-0/+1
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* More progress in FIRRTL back-endClifford Wolf2016-11-183-4/+121
* Progress in FIRRTL back-endClifford Wolf2016-11-184-5/+55
* Added first draft of FIRRTL back-endClifford Wolf2016-11-172-0/+353
* Cleanups and fixed in write_verilog regarding reg initClifford Wolf2016-11-161-15/+61
* Added support for hierarchical defparamsClifford Wolf2016-11-155-17/+65
* Remember global declarations and defines accross read_verilog callsClifford Wolf2016-11-156-8/+23
* Merge pull request #268 from AlexDaniel/masterClifford Wolf2016-11-131-34/+27
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| * Markdownify READMEAleks-Daniel Jakimenko-Aleksejev2016-11-121-34/+27
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* Minor bugfix in submodClifford Wolf2016-11-091-0/+1
* Progress in examples/gowin/Clifford Wolf2016-11-085-21/+95
* Indenting fixes in gowin sim cell libClifford Wolf2016-11-081-20/+28
* Bugfix in "setundef" passClifford Wolf2016-11-081-2/+7
* Added examples/gowin/Clifford Wolf2016-11-076-0/+57
* Implemented "scc -set_attr"Clifford Wolf2016-11-061-22/+32
* Bugfix in "scc" commandClifford Wolf2016-11-061-9/+11
* Fixed anonymous genblock object namesClifford Wolf2016-11-041-1/+1
* Added hex constant support to write_verilogClifford Wolf2016-11-032-5/+63
* We are now in 0.7+ developmentClifford Wolf2016-11-031-1/+1
* Yosys 0.7Clifford Wolf2016-11-031-1/+1
* Bugfix in "hierarchy -check"Clifford Wolf2016-11-021-1/+1
* Updated command reference in manualClifford Wolf2016-11-021-100/+568
* Changelog for Yosys 0.7Clifford Wolf2016-11-021-0/+99
* Added support for fsm_encoding="user"Clifford Wolf2016-11-021-3/+3
* Added "fsm_expand -full"Clifford Wolf2016-11-022-17/+35
* Some fixes in handling of signed arraysClifford Wolf2016-11-012-0/+7
* iCE40 flow is not experimental anymoreClifford Wolf2016-11-011-1/+1
* Added initial version of "synth_gowin"Clifford Wolf2016-11-014-0/+266
* Adde "write_verilog -renameprefix -v"Clifford Wolf2016-11-011-5/+23
* Added support for (single-clock) transparent memories to bram testsClifford Wolf2016-11-012-10/+23
* Bugfix in fsm_map for FSMs without reset stateClifford Wolf2016-10-251-1/+2
* Added avail params to ilang format, check module params in 'hierarchy -check'Clifford Wolf2016-10-224-3/+25
* Added "setparam -type"Clifford Wolf2016-10-191-3/+13
* No limit for length of lines in BLIF front-endClifford Wolf2016-10-191-1/+7
* Merge pull request #250 from azonenberg/masterClifford Wolf2016-10-191-4/+35
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| * Fixed typo in last commitAndrew Zonenberg2016-10-181-1/+1
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