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authorClifford Wolf <clifford@clifford.at>2016-11-08 18:54:00 +0100
committerClifford Wolf <clifford@clifford.at>2016-11-08 18:54:00 +0100
commite9d73d2ee0b199f4aec4939a54b9ae5d9077323c (patch)
treebca912868b19888545ceb8be7e37d3010b5ca4af
parent97ac77513fa29d0c23ee3453247d214f986d5e19 (diff)
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Indenting fixes in gowin sim cell lib
-rw-r--r--techlibs/gowin/cells_sim.v48
1 files changed, 28 insertions, 20 deletions
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index 3a09c157f..947942626 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -1,51 +1,59 @@
module LUT1(output F, input I0);
- parameter [1:0] INIT = 0;
- assign F = I0 ? INIT[1] : INIT[0];
+ parameter [1:0] INIT = 0;
+ assign F = I0 ? INIT[1] : INIT[0];
endmodule
module LUT2(output F, input I0, I1);
- parameter [3:0] INIT = 0;
- wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
- assign F = I0 ? s1[1] : s1[0];
+ parameter [3:0] INIT = 0;
+ wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
+ assign F = I0 ? s1[1] : s1[0];
endmodule
module LUT3(output F, input I0, I1, I2);
- parameter [7:0] INIT = 0;
- wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
- wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
- assign F = I0 ? s1[1] : s1[0];
+ parameter [7:0] INIT = 0;
+ wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
+ wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
+ assign F = I0 ? s1[1] : s1[0];
endmodule
module LUT4(output F, input I0, I1, I2, I3);
- parameter [15:0] INIT = 0;
- wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
- wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
- wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
- assign F = I0 ? s1[1] : s1[0];
+ parameter [15:0] INIT = 0;
+ wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
+ wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
+ wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
+ assign F = I0 ? s1[1] : s1[0];
endmodule
module DFF (output reg Q, input CLK, D);
- always @(posedge C)
+ parameter [0:0] INIT = 1'b0;
+ initial Q = INIT;
+ always @(posedge CLK)
Q <= D;
endmodule
module DFFN (output reg Q, input CLK, D);
- always @(negedge C)
+ parameter [0:0] INIT = 1'b0;
+ initial Q = INIT;
+ always @(negedge CLK)
Q <= D;
endmodule
module VCC(output V);
- assign V = 1;
+ assign V = 1;
endmodule
module GND(output G);
- assign G = 0;
+ assign G = 0;
endmodule
module IBUF(output O, input I);
- assign O = I;
+ assign O = I;
endmodule
module OBUF(output O, input I);
- assign O = I;
+ assign O = I;
+endmodule
+
+module GSR (input GSRI);
+ wire GSRO = GSRI;
endmodule