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* verilog_backend: add `-sv` option, make `-o <filename>.sv` work.whitequark2020-07-162-11/+20
* intel: Use dfflegalize.Marcelina Kościelnicka2020-07-138-178/+17
* Revert "intel_alm: direct M10K instantiation"Lofty2020-07-138-128/+38
* Merge pull request #2263 from whitequark/cxxrtl-capi-eval-commitwhitequark2020-07-132-0/+20
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| * cxxrtl: expose eval() and commit() via the C API.whitequark2020-07-122-0/+20
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* xilinx: Fix srl regression.Marcelina Kościelnicka2020-07-122-2/+43
* proc_dlatch: Remove init values for combinatorial processes.Marcelina Kościelnicka2020-07-121-0/+33
* dfflegalize: Gather init values from all wires.Marcelina Kościelnicka2020-07-121-1/+1
* Merge pull request #2256 from YosysHQ/claire/fix2241clairexen2020-07-101-0/+2
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| * Add AST_EDGE support to AstNode::detect_latch(), fixes #2241Claire Wolf2020-07-101-0/+2
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* Merge pull request #2255 from whitequark/bison-Werror-conflictswhitequark2020-07-096-69/+11
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| * verilog_parser: turn S/R and R/R conflicts into hard errors.whitequark2020-07-091-1/+1
| * Revert PRs #2203 and #2244.whitequark2020-07-095-68/+10
* | Merge pull request #2254 from whitequark/cxxrtl-extern-cwhitequark2020-07-091-0/+1
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| * | cxxrtl: add missing extern "C".whitequark2020-07-091-0/+1
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* / sf2: Use dfflegalize.Marcelina Kościelnicka2020-07-092-44/+13
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* xilinx: Use dfflegalize.Marcelina Kościelnicka2020-07-096-484/+131
* dfflibmap: Refactor to use dfflegalize internally.Marcelina Kościelnicka2020-07-095-212/+214
* Fix issue #2251 (#2252)Lucas Castro2020-07-091-1/+1
* clkbufmap: improve input pad handling.Marcelina Kościelnicka2020-07-092-17/+118
* Merge pull request #2244 from antmicro/logicclairexen2020-07-094-7/+31
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| * Add logic param and integer bad syntax testsKamil Rakoczy2020-07-063-0/+21
| * Support logic typed parametersLukasz Dalek2020-07-061-7/+10
* | clk2fflogic: Consistently treat async control signals as negative hold.Marcelina Kościelnicka2020-07-098-88/+82
* | dfflegalize: Add special support for const-D latches.Marcelina Kościelnicka2020-07-092-0/+71
* | Merge pull request #2246 from YosysHQ/mwk/dfflegalize-typowhitequark2020-07-071-1/+1
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| * | dfflegalize: typo fixMarcelina Kościelnicka2020-07-071-1/+1
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* | efinix: Use dfflegalize.Marcelina Kościelnicka2020-07-062-15/+53
* | gowin: Use dfflegalize.Marcelina Kościelnicka2020-07-064-158/+49
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* intel_alm: direct M10K instantiationDan Ravensloft2020-07-058-38/+128
* Naming fixes.Marcelina Kościelnicka2020-07-052-2/+2
* synth_gowin: ABC9 supportDan Ravensloft2020-07-053-35/+345
* intel_alm: add Cyclone 10 GX testsDan Ravensloft2020-07-0511-2/+236
* Merge pull request #2236 from YosysHQ/mwk/dfflegalize-ice40Marcelina Kościelnicka2020-07-054-208/+24
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| * ice40: Use dfflegalize.Marcelina Kościelnicka2020-07-054-208/+24
* | ecp5: Use dfflegalize.Marcelina Kościelnicka2020-07-054-254/+96
* | Merge pull request #2227 from Ravenslofty/ccachewhitequark2020-07-051-0/+5
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| * | Add option to use ccache when buildingDan Ravensloft2020-07-041-0/+5
* | | Merge pull request #2232 from YosysHQ/mwk/gowin-sim-initMarcelina Kościelnicka2020-07-051-8/+8
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| * | | gowin: Fix INIT values in sim library.Marcelina Kościelnicka2020-07-051-8/+8
* | | | dfflegalize: Prefer mapping dff to sdff before adffMarcelina Kościelnicka2020-07-051-1/+1
* | | | opt_expr: Fix crash on $mul optimization with more zeros removed than Y has.Marcelina Kościelnicka2020-07-052-0/+24
* | | | intel_alm: DSP inferenceDan Ravensloft2020-07-057-9/+209
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* | | gowin: replace determine_init with setundefDan Ravensloft2020-07-043-74/+1
* | | synth_intel_alm: Use dfflegalize.Marcelina Kościelnicka2020-07-043-122/+10
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* | Improve MISTRAL_FF specify rulesDan Ravensloft2020-07-042-6/+6
* | tests: update fsm.ys resource countEddie Hung2020-07-041-4/+4
* | abc9: only techmap (* abc9_flop *) modulesEddie Hung2020-07-041-1/+1
* | intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FFEddie Hung2020-07-042-47/+2
* | abc9: techmap from user design to allow abc9_flop modules to be composedEddie Hung2020-07-041-1/+1
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