iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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* \|	Merge pull request #2081 from YosysHQ/eddie/blackbox_ast	Eddie Hung	2020-05-30	1	-25/+1
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\| * \|	blackbox: re-use existing Module::makeblackbox() method	Eddie Hung	2020-05-25	1	-25/+1
* \| \|	Merge pull request #2018 from boqwxp/qbfsat-timeout	clairexen	2020-05-30	3	-18/+84
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\| * \| \|	smtbmc: Remove superfluous `yosys-smt2-timeout` file macro.	Alberto Gonzalez	2020-05-29	1	-4/+0
\| * \| \|	smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, a...	Alberto Gonzalez	2020-05-25	3	-18/+88
* \| \| \|	Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic	clairexen	2020-05-29	3	-2/+11
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\| * \| \| \|	ast/simplify: don't bitblast async ROMs declared as `logic`.	whitequark	2020-05-05	3	-2/+11
* \| \| \| \|	Merge pull request #1885 from Xiretza/mod-rem-cells	clairexen	2020-05-29	26	-40/+540
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\| * \| \| \| \|	Document division and modulo cells	Xiretza	2020-05-28	1	-0/+23
\| * \| \| \| \|	Update CHANGELOG	Xiretza	2020-05-28	1	-0/+1
\| * \| \| \| \|	Add comments for mod/div semantics to rtlil.h	Xiretza	2020-05-28	1	-0/+4
\| * \| \| \| \|	Expand tests/simple/constmuldivmod.v	Xiretza	2020-05-28	1	-1/+41
\| * \| \| \| \|	Add flooring division operator	Xiretza	2020-05-28	19	-24/+213
\| * \| \| \| \|	Add flooring modulo operator	Xiretza	2020-05-28	23	-37/+280
* \| \| \| \| \|	Merge pull request #2092 from whitequark/rtlil-no-space-control	clairexen	2020-05-29	2	-6/+11
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\| * \| \| \| \| \|	Restrict RTLIL::IdString to not contain whitespace or control chars.	whitequark	2020-05-29	2	-6/+11
* \| \| \| \| \| \|	Merge pull request #2017 from boqwxp/qbfsat-cvc4	clairexen	2020-05-29	1	-2/+6
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\| * \| \| \| \| \|	qbfsat: Add support for CVC4.	Alberto Gonzalez	2020-05-25	1	-2/+6
* \| \| \| \| \| \|	Merge pull request #2016 from boqwxp/qbfsat-yices	clairexen	2020-05-29	2	-21/+52
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\| * \| \| \| \| \|	qbfsat: Move SMT2 info statements back to the top of the file.	Alberto Gonzalez	2020-05-25	1	-3/+3
\| * \| \| \| \| \|	qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices th...	Alberto Gonzalez	2020-05-25	2	-23/+54
* \| \| \| \| \| \|	Merge pull request #2097 from whitequark/ilang_lexer-fix-erange	whitequark	2020-05-29	1	-1/+3
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\| * \| \| \| \| \| \|	ilang_lexer: fix check for out of range literal.	whitequark	2020-05-29	1	-1/+3
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* \| \| \| \| \| \|	Merge pull request #2033 from boqwxp/cleanup-verilog-lexer	whitequark	2020-05-29	1	-6/+5
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\| * \| \| \| \| \|	verilog: Move lexer location variables from global namespace to `VERILOG_FRON...	Alberto Gonzalez	2020-05-06	1	-6/+5
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* \| \| \| \| \|	Merge pull request #2095 from rswarbrick/hier-typo	whitequark	2020-05-28	1	-2/+2
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\| * \| \| \| \| \|	Fix small typos in documentation for hierarchy command	Rupert Swarbrick	2020-05-28	1	-2/+2
* \| \| \| \| \| \|	Merge pull request #2091 from boqwxp/printattrs	whitequark	2020-05-28	3	-0/+105
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\| * \| \| \| \| \|	printattrs: Simplify `get_indent_str()`.	Alberto Gonzalez	2020-05-28	1	-3/+1
\| * \| \| \| \| \|	printattrs: Refactor indentation string building for clarity.	Alberto Gonzalez	2020-05-27	1	-5/+11
\| * \| \| \| \| \|	printattrs: Add test.	Alberto Gonzalez	2020-05-27	1	-0/+14
\| * \| \| \| \| \|	printattrs: Use `flags` to pretty-print the `RTLIL::Const` appropriately.	Alberto Gonzalez	2020-05-27	1	-8/+15
\| * \| \| \| \| \|	misc: Add `printattrs` command.	Alberto Gonzalez	2020-05-27	2	-0/+80
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* \| \| \| \| \|	Merge pull request #2051 from Xiretza/makefile-cd-warning	whitequark	2020-05-28	1	-1/+1
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\| * \| \| \| \| \|	Suppress warning during initial clone of ABC repo	Xiretza	2020-05-14	1	-1/+1
* \| \| \| \| \| \|	Merge pull request #2031 from epfl-vlsc/master	whitequark	2020-05-28	1	-1/+40
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\| * \| \| \| \| \| \|	Formatting fixes	Sahand Kashani	2020-05-06	1	-14/+7
\| * \| \| \| \| \| \|	Add extmodule support to firrtl backend	Sahand Kashani	2020-05-06	1	-1/+47
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* \| \| \| \| \| \|	Merge pull request #2063 from boqwxp/techmapped-firrtl	whitequark	2020-05-28	1	-10/+12
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\| * \| \| \| \| \| \|	firrtl: Accept techmapped cell types in FIRRTL backend.	Alberto Gonzalez	2020-05-17	1	-10/+12
* \| \| \| \| \| \| \|	Merge pull request #2088 from rswarbrick/count-at	whitequark	2020-05-28	1	-2/+8
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\| * \| \| \| \| \| \| \|	Minor optimisation in Module::wire() and Module::cell()	Rupert Swarbrick	2020-05-26	1	-2/+8
* \| \| \| \| \| \| \| \|	Merge pull request #2087 from rswarbrick/lex-warn	whitequark	2020-05-28	1	-1/+3
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\| * \| \| \| \| \| \| \| \|	Silence spurious warning in Verilog lexer when compiling with GCC	Rupert Swarbrick	2020-05-26	1	-1/+3
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* \| \| \| \| \| \| \| \|	Merge pull request #2086 from rswarbrick/sigbit	whitequark	2020-05-28	1	-2/+1
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\| * \| \| \| \| \| \| \| \|	Use default copy constructor for RTLIL::SigBit	Rupert Swarbrick	2020-05-26	1	-2/+1
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* \| \| \| \| \| \| \| \|	Merge pull request #2084 from rswarbrick/c_str	whitequark	2020-05-28	1	-2/+2
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\| * \| \| \| \| \| \| \|	Use c_str(), not str() for IdString/std::string == and != operators	Rupert Swarbrick	2020-05-26	1	-2/+2
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* \| \| \| \| \| \| \|	Merge pull request #2090 from whitequark/cxxrtl-fixes	whitequark	2020-05-26	1	-7/+13
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\| * \| \| \| \| \| \|	cxxrtl: make logging a little bit nicer.	whitequark	2020-05-26	1	-2/+10