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* Implemented basic real arithmeticClifford Wolf2014-06-143-6/+51
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* Added real->int convertion in ast genrtlilClifford Wolf2014-06-141-0/+12
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* Added Verilog lexer and parser support for real valuesClifford Wolf2014-06-134-3/+31
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* Added read_verilog -sv options, added support for bit, logic,Clifford Wolf2014-06-127-8/+52
| | | | allways_ff, always_comb, and always_latch
* Now we are in Yoys 0.3.0+ developmentClifford Wolf2014-06-082-1/+7
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* Tagging Yosys 0.3.0Clifford Wolf2014-06-082-3/+47
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* Updated ABC to 7600ffb9340cClifford Wolf2014-06-081-1/+1
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* added tests for new verilog featuresClifford Wolf2014-06-072-6/+37
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* fixed cell array handling of positional argumentsClifford Wolf2014-06-071-2/+11
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* Add support for cell arraysClifford Wolf2014-06-076-1/+70
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* Added support for repeat stmt in const functionsClifford Wolf2014-06-071-0/+19
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* further improved const function supportClifford Wolf2014-06-073-17/+22
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* made the generate..endgenrate keywords optionalClifford Wolf2014-06-061-4/+8
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* improved const function supportClifford Wolf2014-06-063-5/+41
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* fix functions with no block (but single statement, loop, etc.)Clifford Wolf2014-06-061-11/+4
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* Added tests/simple/repwhile.vClifford Wolf2014-06-061-0/+20
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* improved ast simplify of const functionsClifford Wolf2014-06-061-7/+28
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* added while and repeat support to verilog parserClifford Wolf2014-06-064-1/+31
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* Improved error message for options after front-end filename argumentsClifford Wolf2014-06-042-1/+5
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* added tee cmdClifford Wolf2014-06-032-0/+89
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* Fixed log messages in memory_dffClifford Wolf2014-06-011-0/+2
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* Updated ABC to rev fa4404b395f0Clifford Wolf2014-05-291-1/+1
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* Merge pull request #36 from hansiglaser/masterClifford Wolf2014-05-294-8/+54
|\ | | | | Various changes merged
| * added log_header to miter and expose pass, show cell type for exposed portsJohann Glaser2014-05-282-3/+9
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| * new flags -ignore_miss_func and -ignore_miss_dir for read_libertyJohann Glaser2014-05-281-4/+40
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| * be more verbose when techmap yielded processesJohann Glaser2014-05-261-1/+5
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* Fixed bug in opt_reduce (see vloghammer issue_044)Clifford Wolf2014-05-121-1/+4
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* fixed syntax error in dot file created by "show" commandClifford Wolf2014-05-101-1/+1
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-05-095-114/+87
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| * Progress in presentationClifford Wolf2014-05-061-8/+63
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| * Improved ezsat stand-alone testsClifford Wolf2014-05-064-106/+24
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* | Updated ABC to 67c84cdd49e4Clifford Wolf2014-05-091-1/+1
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* workaround for OpenBSD 'stdout' implementationClifford Wolf2014-05-031-1/+2
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* workaround for OpenBSD 'stdin' implementationClifford Wolf2014-05-021-1/+2
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* Merge pull request #35 from bentley/doxClifford Wolf2014-05-022-32/+32
|\ | | | | Typos and grammar fixes through chapter 4.
| * Typos and grammar fixes through chapter 4.Anthony J. Bentley2014-05-022-32/+32
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* Fixed clang -Wdeprecated-register warningsClifford Wolf2014-04-202-0/+12
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* Replaced depricated %name-prefix= bison directiveClifford Wolf2014-04-202-2/+2
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* minisat compile fixClifford Wolf2014-04-203-2/+25
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* Updated READMEClifford Wolf2014-04-181-18/+11
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* Merge pull request #33 from bentley/doxClifford Wolf2014-04-113-21/+21
|\ | | | | Typos and grammar fixes through chapter 2.
| * Typos and grammar fixes through chapter 2.Anthony J. Bentley2014-04-113-21/+21
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* Merge pull request #31 from bentley/posix-rmClifford Wolf2014-04-053-6/+6
|\ | | | | Remove non-POSIX 'rm -v'.
| * POSIX find requires a path argument.Anthony J. Bentley2014-04-042-2/+2
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| * Remove non-POSIX 'rm -v'.Anthony J. Bentley2014-04-041-4/+4
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* Added SIMLIB_NOLUT to simlib.vClifford Wolf2014-04-021-0/+2
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* Added SIMLIB_NOSR to simlib.vClifford Wolf2014-04-021-0/+6
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* Added support for dlatchsr cellsClifford Wolf2014-03-315-1/+207
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* Fixed mapping of Verific WIDE_DFFRS operatorClifford Wolf2014-03-201-2/+2
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* Fixed mapping of Verific FADD primitive with unconnected outputsClifford Wolf2014-03-201-4/+5
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