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* Hotfix for 4c82ddfClifford Wolf2019-02-211-11/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #822 from litghost/expand_setundefClifford Wolf2019-02-211-0/+29
|\ | | | | Add -params mode to force undef parameters in selected cells.
| * Add -params mode to force undef parameters in selected cells.Keith Rothman2019-02-211-0/+29
|/ | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #818 from YosysHQ/clifford/dffsrfixClifford Wolf2019-02-211-6/+7
|\ | | | | Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816
| * Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816Clifford Wolf2019-02-211-6/+7
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #786 from YosysHQ/pmgenClifford Wolf2019-02-2114-59/+1851
|\ \ | | | | | | Pattern Matcher Generator and iCE40 DSP Mapper
| * | Fix typo in passes/pmgen/README.mdClifford Wolf2019-02-211-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Bugfix in ice40_dspClifford Wolf2019-02-213-22/+35
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add ice40 test_dsp_map test case generatorClifford Wolf2019-02-202-0/+99
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add "synth_ice40 -dsp"Clifford Wolf2019-02-202-7/+31
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add FF support to wreduceClifford Wolf2019-02-202-1/+73
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Improve iCE40 SB_MAC16 modelClifford Wolf2019-02-205-121/+179
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Detect and reject cases that do not map well to iCE40 DSPs (yet)Clifford Wolf2019-02-202-2/+17
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add first draft of functional SB_MAC16 modelClifford Wolf2019-02-194-53/+467
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add actual DSP inference to ice40_dsp passClifford Wolf2019-02-173-24/+214
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge branch 'master' of github.com:YosysHQ/yosys into pmgenClifford Wolf2019-02-1728-199/+627
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| * | | Progress in pmgenClifford Wolf2019-01-151-3/+11
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Progress in pmgen, add pmgen READMEClifford Wolf2019-01-153-14/+260
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Fix pmgen "reject" statementClifford Wolf2019-01-151-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Progress in pmgenClifford Wolf2019-01-153-36/+139
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Progress in pmgenClifford Wolf2019-01-153-21/+157
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Progress in pmgenClifford Wolf2019-01-155-8/+347
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add mockup .pmg (pattern matcher generator) fileClifford Wolf2019-01-151-0/+75
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge pull request #821 from eddiehung/dff_initClifford Wolf2019-02-211-4/+2
|\ \ \ \ | |_|_|/ |/| | | Revert "Add -B option to autotest.sh to append to backend_opts"
| * | | Revert "Add -B option to autotest.sh to append to backend_opts"Eddie Hung2019-02-211-4/+2
| | | | | | | | | | | | | | | | This reverts commit 281f2aadcab01465f83a3f3a697eec42503e9f8b.
* | | | Merge pull request #817 from eddiehung/dff_initEddie Hung2019-02-201-21/+0
|\| | | | | | | | | | | Cleanup #805
| * | | Remove simple_defparam testsEddie Hung2019-02-201-21/+0
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* | | | Merge pull request #805 from eddiehung/dff_initEddie Hung2019-02-194-2/+76
|\| | | | |_|/ |/| | write_verilog to write initial statement for initial flop state
| * | Instead of INIT param on cells, use initial statement with hier ref asEddie Hung2019-02-171-18/+13
| | | | | | | | | | | | per @cliffordwolf
| * | Revert "Add INIT parameter to all ff/latch cells"Eddie Hung2019-02-172-86/+43
| | | | | | | | | | | | This reverts commit 742b4e01b498ae2e735d40565f43607d69a015d8.
| * | Merge https://github.com/YosysHQ/yosys into dff_initEddie Hung2019-02-179-100/+345
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* | | Merge pull request #811 from ucb-bar/firrtlfixesClifford Wolf2019-02-176-56/+298
|\ \ \ | | | | | | | | Update cells supported for verilog to FIRRTL conversion.
| * | | Removed unused variables, functions.Jim Lawson2019-02-151-20/+0
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| * | | Append (instead of over-writing) EXTRA_FLAGSJim Lawson2019-02-151-1/+1
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| * | | Update cells supported for verilog to FIRRTL conversion.Jim Lawson2019-02-155-55/+317
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issue warning messages for missing parameterized modules and attempts to set initial values. Replace simple "if (cell-type)" with "else if" chain. Fix FIRRTL shift handling. Add support for parameterized modules, $shift, $shiftx. Handle default output file. Deal with no top module. Automatically run pmuxtree pass. Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk. Support FIRRTL regression testing in tests/tools/autotest.sh Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.
* | | Fix sign handling of real constantsClifford Wolf2019-02-131-5/+4
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge pull request #802 from whitequark/write_verilog_async_mem_portsClifford Wolf2019-02-121-38/+41
|\ \ \ | | | | | | | | write_verilog: correctly emit asynchronous transparent ports
| * | | write_verilog: correctly emit asynchronous transparent ports.whitequark2019-01-291-38/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes two related issues: * For asynchronous ports, clock is no longer added to domain list. (This would lead to absurd constructs like `always @(posedge 0)`. * The logic to distinguish synchronous and asynchronous ports is changed to correctly use or avoid clock in all cases. Before this commit, the following RTLIL snippet (after memory_collect) cell $memrd $2 parameter \MEMID "\\mem" parameter \ABITS 2 parameter \WIDTH 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 1 parameter \TRANSPARENT 1 connect \CLK 1'0 connect \EN 1'1 connect \ADDR \mem_r_addr connect \DATA \mem_r_data end would lead to invalid Verilog: reg [1:0] _0_; always @(posedge 1'h0) begin _0_ <= mem_r_addr; end assign mem_r_data = mem[_0_]; Note that there are two potential pitfalls remaining after this change: * For asynchronous ports, the \EN input and \TRANSPARENT parameter are silently ignored. (Per discussion in #760 this is the correct behavior.) * For synchronous transparent ports, the \EN input is ignored. This matches the behavior of the $mem simulation cell. Again, see #760.
* | | | Merge pull request #806 from daveshah1/fsm_opt_no_resetClifford Wolf2019-02-121-1/+2
|\ \ \ \ | | | | | | | | | | fsm_opt: Fix runtime error for FSMs without a reset state
| * | | | fsm_opt: Fix runtime error for FSMs without a reset stateDavid Shah2019-02-071-1/+2
|/ / / / | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | Cope WIDTH of ff/latch cells is default of zeroEddie Hung2019-02-061-6/+6
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| | * | Remove check for cell->name[0] == '$'Eddie Hung2019-02-061-1/+1
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| | * | RefactorEddie Hung2019-02-061-21/+5
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| | * | write_verilog to cope with init attr on q when -noexprEddie Hung2019-02-061-2/+32
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| | * | Add INIT parameter to all ff/latch cellsEddie Hung2019-02-062-43/+86
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| | * | Add tests for simple cases using defparamEddie Hung2019-02-061-0/+21
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| | * | Add -B option to autotest.sh to append to backend_optsEddie Hung2019-02-061-2/+4
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| | * | Extend testcaseEddie Hung2019-02-061-2/+34
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| | * | Add testcaseEddie Hung2019-02-061-0/+10
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* | | Add missing blackslash-to-slash convertion to smtio.py (matching ↵Clifford Wolf2019-02-061-1/+1
|/ / | | | | | | | | | | Smt2Worker::get_id() behavior) Signed-off-by: Clifford Wolf <clifford@clifford.at>
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