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* Fix spelling in pmgen/README.mdEddie Hung2019-03-051-2/+2
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* Improve igloo2 exmapleClifford Wolf2019-03-054-8/+16
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #842 from litghost/merge_upstreamClifford Wolf2019-03-0510-176/+570
|\ | | | | Changes required for VPR place and route in synth_xilinx
| * Revert BRAM WRITE_MODE changes.Keith Rothman2019-03-041-12/+12
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Revert FF models to include IS_x_INVERTED parameters.Keith Rothman2019-03-011-6/+34
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Use singular for disabling of DRAM or BRAM inference.Keith Rothman2019-03-012-26/+19
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Modify arguments to match existing style.Keith Rothman2019-03-012-11/+11
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Changes required for VPR place and route synth_xilinx.Keith Rothman2019-03-0112-227/+600
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #850 from daveshah1/ecp5_warn_conflictClifford Wolf2019-03-051-2/+7
|\ \ | | | | | | ecp5: Demote conflicting FF init values to a warning
| * | ecp5: Demote conflicting FF init values to a warningDavid Shah2019-03-041-2/+7
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Add missing newlineClifford Wolf2019-03-051-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge pull request #851 from kprasadvnsi/masterClifford Wolf2019-03-057-0/+55
|\ \ \ | | | | | | | | Added examples/anlogic/
| * | | Added examples/anlogic/Kali Prasad2019-03-047-0/+55
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* | | | Merge pull request #852 from ucb-bar/firrtlfixesClifford Wolf2019-03-052-2/+2
|\ \ \ \ | | | | | | | | | | Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails
| * | | | Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v failsJim Lawson2019-03-042-2/+2
| |/ / / | | | | | | | | | | | | Mark dff_init.v as expected to fail since it uses "initial value".
* / / / Use "write_edif -pvector bra" for Xilinx EDIF filesClifford Wolf2019-03-051-1/+1
|/ / / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Improve igloo2 exampleClifford Wolf2019-03-032-3/+10
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Update igloo2 example to Libero v12.0Clifford Wolf2019-03-032-6/+5
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge pull request #848 from YosysHQ/clifford/fix763Clifford Wolf2019-03-021-1/+5
|\ \ \ | | | | | | | | Fix error for wire decl in always block, fixes 763
| * | | Fix error for wire decl in always block, fixes #763Clifford Wolf2019-03-021-1/+5
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge pull request #849 from YosysHQ/clifford/dynportsClifford Wolf2019-03-024-1/+24
|\ \ \ \ | |/ / / |/| | | Only run derive on blackbox modules when ports have dynamic size
| * | | Only run derive on blackbox modules when ports have dynamic sizeClifford Wolf2019-03-024-1/+24
|/ / / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Fix $global_clock handling vs autowireClifford Wolf2019-03-021-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge pull request #847 from YosysHQ/clifford/fix785Clifford Wolf2019-03-021-0/+35
|\ \ \ | | | | | | | | Fix $readmem[hb] for mem2reg memories, fixes #785
| * | | Fix $readmem[hb] for mem2reg memories, fixes #785Clifford Wolf2019-03-021-0/+35
|/ / / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge pull request #843 from YosysHQ/clifford/mem2regconstidxClifford Wolf2019-03-022-0/+13
|\ \ \ | | | | | | | | Use mem2reg on memories that only have constant-index write ports
| * | | Use mem2reg on memories that only have constant-index write portsClifford Wolf2019-03-012-0/+13
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge pull request #845 from YosysHQ/clifford/travisnomacosClifford Wolf2019-03-021-5/+5
|\ \ \ \ | |_|/ / |/| | | Disable macOS builds in Travis
| * | | Disable macOS builds in TravisClifford Wolf2019-03-021-5/+5
|/ / / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Try again for passes/pmgen/ice40_dsp_pm.h ruleLarry Doolittle2019-03-012-8/+9
| | | | | | | | | | | | Tested on both in-tree and out-of-tree builds
* | | Minor improvements in READMEClifford Wolf2019-03-011-3/+16
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* / Fix "write_edif -gndvccy"Clifford Wolf2019-03-011-1/+1
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #841 from mmicko/masterClifford Wolf2019-03-011-2/+3
|\ | | | | Fix ECP5 cells_sim for iverilog
| * Fix ECP5 cells_sim for iverilogMiodrag Milanovic2019-03-011-2/+3
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* Improve "read" error msgClifford Wolf2019-02-281-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_modeClifford Wolf2019-02-281-2/+2
|\ | | | | ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
| * ice40: use 2 bits for READ/WRITE MODE for SB_RAM mapElms2019-02-281-2/+2
| | | | | | | | | | | | EBLIF output .param will only use necessary 2 bits Signed-off-by: Elms <elms@freshred.net>
* | Hotfix for "make test"Clifford Wolf2019-02-281-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #837 from YosysHQ/clifford/fix835Clifford Wolf2019-02-281-5/+24
|\ \ | | | | | | Fix multiple issues in wreduce FF handling, fixes #835
| * | Fix multiple issues in wreduce FF handling, fixes #835Clifford Wolf2019-02-281-5/+24
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #834 from YosysHQ/clifford/siminitClifford Wolf2019-02-282-3/+12
|\ \ | | | | | | Add "write_verilog -siminit"
| * | Add "write_verilog -siminit"Clifford Wolf2019-02-282-3/+12
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Reduce amount of trailing whitespace in code baseLarry Doolittle2019-02-289-29/+29
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* | Fix pmgen for in-tree buildsClifford Wolf2019-02-282-8/+9
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #794 from daveshah1/ecp5improveClifford Wolf2019-02-287-12/+388
|\ \ | | | | | | ECP5 Improvements
| * | ecp5: Compatibility with Migen AsyncResetSynchronizerDavid Shah2019-02-252-0/+20
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | ecp5: Add DDRDLLADavid Shah2019-02-191-0/+9
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | ecp5: Add DELAYF/DELAYG blackboxesDavid Shah2019-02-191-0/+18
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | ecp5: Add ECLKSYNCB blackboxDavid Shah2019-02-131-1/+7
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | ecp5: Full set of IO-related blackboxesDavid Shah2019-02-121-0/+102
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
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