| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | - Makefile: export PATH=${DESTDIR}/bin:$(PATH) and (DY)LD_LIBRARY_PATH, to m... | Siesh1oo | 2014-03-13 | 1 | -1/+5 |
| * | - Makefile: resolve merge conflict. | Siesh1oo | 2014-03-13 | 1 | -5/+23 |
| * | Some fixes in libs/minisat (thanks to Siesh1oo) | Clifford Wolf | 2014-03-12 | 3 | -9/+10 |
| * | - kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_shar... | Siesh1oo | 2014-03-12 | 5 | -37/+44 |
| * | Fixed dependencies of "make test" | Clifford Wolf | 2014-03-12 | 1 | -1/+1 |
| * | Added libs/minisat (copy of minisat git master) | Clifford Wolf | 2014-03-12 | 28 | -28/+5025 |
| * | OSX compatible creation of stdcells.inc, using code from github.com/Siesh1oo/... | Clifford Wolf | 2014-03-11 | 1 | -2/+3 |
| * | Merged addition of SED makefile variable from github.com/Siesh1oo/yosys | Clifford Wolf | 2014-03-11 | 2 | -2/+3 |
| * | Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys | Clifford Wolf | 2014-03-11 | 11 | -13/+52 |
| * | Added support for `line compiler directive | Clifford Wolf | 2014-03-11 | 1 | -0/+11 |
| * | Fixed memory corruption in passes/abc/blifparse.cc | Clifford Wolf | 2014-03-11 | 1 | -1/+1 |
| * | Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.sh | Clifford Wolf | 2014-03-11 | 1 | -1/+1 |
| * | Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog) | Clifford Wolf | 2014-03-11 | 1 | -1/+1 |
| * | Fixed a typo in RTLIL::Module::addReduce... | Clifford Wolf | 2014-03-10 | 1 | -5/+5 |
| * | Improved verific command (added support for some operators) | Clifford Wolf | 2014-03-10 | 1 | -2/+160 |
| * | Improvements in verific command | Clifford Wolf | 2014-03-10 | 1 | -59/+39 |
| * | Added RTLIL::Module::add... helper methods | Clifford Wolf | 2014-03-10 | 2 | -0/+293 |
| * | Added "verific" command | Clifford Wolf | 2014-03-09 | 3 | -2/+501 |
| * | Fixed dumping of timing() { .. } block in libparse | Clifford Wolf | 2014-03-09 | 1 | -2/+3 |
| * | Verbose reading of liberty and constr files in ABC pass | Clifford Wolf | 2014-03-09 | 1 | -2/+2 |
| * | Fixed bug in freduce command | Clifford Wolf | 2014-03-07 | 1 | -0/+30 |
| * | Some minor code cleanups in freduce command | Clifford Wolf | 2014-03-07 | 1 | -5/+5 |
| * | Bugfix in ilang frontend autoidx recovery | Clifford Wolf | 2014-03-07 | 1 | -2/+2 |
| * | Use log_abort() and log_assert() in BTOR backend | Clifford Wolf | 2014-03-07 | 1 | -18/+17 |
| * | Added freduce -dump | Clifford Wolf | 2014-03-06 | 1 | -1/+24 |
| * | Added freduce -stop | Clifford Wolf | 2014-03-06 | 1 | -3/+18 |
| * | Fixed gcc compiler warning | Clifford Wolf | 2014-03-06 | 1 | -1/+2 |
| * | Fixed undef handling in opt_reduce | Clifford Wolf | 2014-03-06 | 1 | -2/+2 |
| * | Fixes for improved techmap of shifts with large B inputs | Clifford Wolf | 2014-03-06 | 1 | -8/+8 |
| * | Fixed use of frozen literals in SatGen | Clifford Wolf | 2014-03-06 | 1 | -3/+2 |
| * | Strictly zero-extend unsigned A-inputs of shift operations in techmap | Clifford Wolf | 2014-03-06 | 1 | -4/+4 |
| * | Added techmap -max_iter option | Clifford Wolf | 2014-03-06 | 1 | -0/+10 |
| * | Improved techmap of shift with wide B inputs | Clifford Wolf | 2014-03-06 | 1 | -13/+37 |
| * | Strictly zero-extend unsigned A-inputs of shift operations | Clifford Wolf | 2014-03-06 | 2 | -3/+3 |
| * | Switched to EZMINISAT_SIMPSOLVER as default SAT solver | Clifford Wolf | 2014-03-05 | 1 | -1/+1 |
| * | Include id2ast pointers when dumping AST | Clifford Wolf | 2014-03-05 | 1 | -0/+6 |
| * | Fixed merging of compatible wire decls in AST frontend | Clifford Wolf | 2014-03-05 | 1 | -1/+4 |
| * | Bugfix in recursive AST simplification | Clifford Wolf | 2014-03-05 | 1 | -10/+22 |
| * | fixed freduce for Minisat::SimpSolver: use frozen_literal() | Clifford Wolf | 2014-03-03 | 1 | -2/+2 |
| * | ezSAT: Added frozen_literal() API | Clifford Wolf | 2014-03-03 | 2 | -0/+16 |
| * | ezSAT: Fixed handling of eliminated Literals, added auto-freeze for expressions | Clifford Wolf | 2014-03-03 | 2 | -8/+23 |
| * | Added ezSAT::eliminated API to help the SAT solver remember eliminated variables | Clifford Wolf | 2014-03-01 | 4 | -3/+17 |
| * | ezSAT bugfix: don't call virtual methods in base class constructor | Clifford Wolf | 2014-03-01 | 2 | -2/+5 |
| * | Removed ezSAT::assumed() API | Clifford Wolf | 2014-03-01 | 3 | -10/+0 |
| * | Removed ezSAT built-in brute-froce solver | Clifford Wolf | 2014-03-01 | 1 | -102/+6 |
| * | Fixed vhdl2verilog temp dir name | Clifford Wolf | 2014-03-01 | 1 | -1/+1 |
| * | Fixed vhdl2verilog help message | Clifford Wolf | 2014-03-01 | 1 | -3/+2 |
| * | Fixed const folding of $bu0 cells | Clifford Wolf | 2014-02-27 | 2 | -1/+2 |
| * | Fixed bit-extending in $mux argument (use $bu0 instead of $pos) | Clifford Wolf | 2014-02-26 | 1 | -5/+5 |
| * | Added support for $bu0 to SatGen | Clifford Wolf | 2014-02-26 | 1 | -4/+4 |
