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author | Clifford Wolf <clifford@clifford.at> | 2014-03-06 13:08:44 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-03-06 13:08:44 +0100 |
commit | 97710ffad5d4750b538dac5f08b77dce37e3cda4 (patch) | |
tree | ed01d47d07ea85576b8080b86223df3b1c5335ea | |
parent | 8406e7f7b6cb8e79f7df02c2c616073a51c1ea9e (diff) | |
download | yosys-97710ffad5d4750b538dac5f08b77dce37e3cda4.tar.gz yosys-97710ffad5d4750b538dac5f08b77dce37e3cda4.tar.bz2 yosys-97710ffad5d4750b538dac5f08b77dce37e3cda4.zip |
Fixed use of frozen literals in SatGen
-rw-r--r-- | kernel/satgen.h | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/kernel/satgen.h b/kernel/satgen.h index 3ae9502f8..bf72a31cb 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -66,13 +66,12 @@ struct SatGen if (c.wire == NULL) { RTLIL::State bit = c.data.bits.at(0); if (model_undef && dup_undef && bit == RTLIL::State::Sx) - vec.push_back(ez->literal()); + vec.push_back(ez->frozen_literal()); else vec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->TRUE : ez->FALSE); } else { std::string name = pf + stringf(c.wire->width == 1 ? "%s" : "%s [%d]", RTLIL::id2cstr(c.wire->name), c.offset); - vec.push_back(ez->literal(name)); - ez->freeze(vec.back()); + vec.push_back(ez->frozen_literal(name)); } return vec; } |