aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* For hier_tree::Elaborate() also include SV root modules (bind)Eddie Hung2019-05-031-23/+36
|
* Fix verific_parameters construction, use attribute to mark top netlistsEddie Hung2019-05-032-8/+12
|
* WIP -chparam support for hierarchy when verificEddie Hung2019-05-033-19/+41
|
* verific_import() changes to avoid ElaborateAll()Eddie Hung2019-05-031-15/+38
|
* Merge pull request #984 from YosysHQ/eddie/fix_982Clifford Wolf2019-05-031-1/+2
|\ | | | | dffinit to do nothing when (* init *) value is 1'bx
| * Revert "synth_xilinx to call dffinit with -noreinit"Eddie Hung2019-05-031-1/+1
| | | | | | | | This reverts commit 1f62dc9081feb4852b1848d01951f631853edb38.
| * If init is 1'bx, do not add to dict as per @cliffordwolfEddie Hung2019-05-031-1/+2
| |
| * Revert "dffinit -noreinit to silently continue when init value is 1'bx"Eddie Hung2019-05-031-12/+4
| | | | | | | | This reverts commit aa081f83c791b1d666214776aaf744a80ce6a690.
| * synth_xilinx to call dffinit with -noreinitEddie Hung2019-05-021-1/+1
| |
| * dffinit -noreinit to silently continue when init value is 1'bxEddie Hung2019-05-021-4/+12
| |
* | Merge pull request #976 from YosysHQ/clifford/fix974Clifford Wolf2019-05-033-0/+25
|\ \ | | | | | | Fix width detection of memory access with bit slice
| * | Add splitcmplxassign test case and silence splitcmplxassign warningClifford Wolf2019-05-012-0/+23
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Fix width detection of memory access with bit slice, fixes #974Clifford Wolf2019-05-011-0/+2
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge pull request #985 from YosysHQ/clifford/fix981Clifford Wolf2019-05-032-44/+81
|\ \ \ | | | | | | | | Improve opt_expr and opt_clean handling of (partially) undriven and/or unused wires
| * | | Improve opt_expr and opt_clean handling of (partially) undriven and/or ↵Clifford Wolf2019-05-032-44/+81
| | |/ | |/| | | | | | | | | | | | | unused wires, fixes #981 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Fix typo in tests/svinterfaces/runone.shClifford Wolf2019-05-031-2/+2
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge pull request #979 from jakobwenzel/svinterfacesTestcaseClifford Wolf2019-05-031-2/+2
|\ \ \ | |/ / |/| | fail svinterfaces testcases on yosys error exit
| * | fail svinterfaces testcases on yosys error exitJakob Wenzel2019-05-021-2/+2
|/ /
* | Merge pull request #963 from YosysHQ/eddie/synth_xilinx_fineClifford Wolf2019-05-023-34/+30
|\ \ | | | | | | Revert synth_xilinx 'fine' label more to how it used to be...
| * | Back to passing all xc7srl tests!Eddie Hung2019-05-011-5/+4
| | |
| * | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fineEddie Hung2019-05-0122-190/+286
| |\ \
| * | | WIPEddie Hung2019-04-281-36/+22
| | | |
| * | | Move neg-pol to pos-pol mapping from ff_map to cells_map.vEddie Hung2019-04-282-9/+12
| | | |
| * | | Revert synth_xilinx 'fine' label more to how it used to be...Eddie Hung2019-04-261-21/+40
| | | |
* | | | Merge pull request #978 from ucb-bar/fmtfirrtlEddie Hung2019-05-011-25/+25
|\ \ \ \ | |_|/ / |/| | | Re-indent firrtl.cc:struct memory - no functional change.
| * | | Re-indent firrtl.cc:struct memory - no functional change.Jim Lawson2019-05-011-25/+25
| | | |
* | | | Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2019-05-0121-176/+273
|\| | |
| * | | Merge branch 'clifford/fix883'Clifford Wolf2019-05-021-0/+1
| |\ \ \
| | * | | Add missing enable_undef to "sat -tempinduct-def", fixes #883Clifford Wolf2019-05-021-0/+1
| |/ / / | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Merge pull request #977 from ucb-bar/fixfirrtlmemClifford Wolf2019-05-013-4/+64
| |\ \ \ | | | | | | | | | | Fix #938 - Crash occurs in case when use write_firrtl command
| | * | | Fix #938 - Crash occurs in case when use write_firrtl commandJim Lawson2019-05-013-4/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing memory initialization. Sanity-check memory parameters. Add Cell pointer to memory object (for error reporting).
| * | | | Fix floating point exception in qwp, fixes #923Clifford Wolf2019-05-011-1/+1
| | |_|/ | |/| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Fix segfault in wreduceClifford Wolf2019-04-301-0/+2
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Disabled "final loop assignment" featureClifford Wolf2019-04-301-0/+2
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #972 from YosysHQ/clifford/fix968Clifford Wolf2019-04-301-0/+7
| |\ \ | | | | | | | | Add final loop variable assignment when unrolling for-loops
| | * | Add final loop variable assignment when unrolling for-loops, fixes #968Clifford Wolf2019-04-301-0/+7
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Merge pull request #966 from YosysHQ/clifford/fix956Clifford Wolf2019-04-303-3/+55
| |\ \ \ | | | | | | | | | | Drive dangling wires with init attr with their init value
| | * | | Add handling of init attributes in "opt_expr -undriven"Clifford Wolf2019-04-302-3/+42
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | Drive dangling wires with init attr with their init value, fixes #956Clifford Wolf2019-04-291-0/+13
| | | | |
| * | | | Merge pull request #962 from YosysHQ/eddie/refactor_synth_xilinxClifford Wolf2019-04-302-156/+101
| |\ \ \ \ | | | | | | | | | | | | Refactor synth_xilinx to auto-generate doc
| | * \ \ \ Merge branch 'master' into eddie/refactor_synth_xilinxClifford Wolf2019-04-309-12/+40
| | |\ \ \ \ | | |/ / / / | |/| | | |
| * | | | | Merge pull request #973 from christian-krieg/feature/python_bindingsClifford Wolf2019-04-303-4/+4
| |\ \ \ \ \ | | | | | | | | | | | | | | Feature/python bindings cleanup
| | * \ \ \ \ Merge branch 'master' of https://github.com/YosysHQ/yosys into ↵Benedikt Tutzer2019-04-3088-320/+2797
| | |\ \ \ \ \ | | | | |_|/ / | | | |/| | | | | | | | | | feature/python_bindings
| | * | | | | Cleaned up root directoryBenedikt Tutzer2019-04-303-4/+4
| | | | | | |
| * | | | | | Include filename in "Executing Verilog-2005 frontend" message, fixes #959Clifford Wolf2019-04-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970Clifford Wolf2019-04-301-1/+1
| | |/ / / / | |/| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | Merge pull request #960 from YosysHQ/eddie/equiv_opt_undefClifford Wolf2019-04-291-3/+16
| |\ \ \ \ \ | | | | | | | | | | | | | | Add -undef option to equiv_opt, passed to equiv_induct
| | * | | | | Add -undef option to equiv_opt, passed to equiv_inductEddie Hung2019-04-261-3/+16
| | | |_|/ / | | |/| | |
| * | | | | Merge pull request #967 from olegendo/depfile_esc_spacesClifford Wolf2019-04-293-2/+17
| |\ \ \ \ \ | | |_|_|_|/ | |/| | | | escape spaces with backslash when writing dep file
| | * | | | fix codestyle formattingOleg Endo2019-04-293-14/+14
| | | | | |
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-17 01:51:45 +0000