| Commit message (Expand) | Author | Age | Files | Lines |
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| * | For hier_tree::Elaborate() also include SV root modules (bind) | Eddie Hung | 2019-05-03 | 1 | -23/+36 |
| * | Fix verific_parameters construction, use attribute to mark top netlists | Eddie Hung | 2019-05-03 | 2 | -8/+12 |
| * | WIP -chparam support for hierarchy when verific | Eddie Hung | 2019-05-03 | 3 | -19/+41 |
| * | verific_import() changes to avoid ElaborateAll() | Eddie Hung | 2019-05-03 | 1 | -15/+38 |
| * | Merge pull request #984 from YosysHQ/eddie/fix_982 | Clifford Wolf | 2019-05-03 | 1 | -1/+2 |
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| | * | Revert "synth_xilinx to call dffinit with -noreinit" | Eddie Hung | 2019-05-03 | 1 | -1/+1 |
| | * | If init is 1'bx, do not add to dict as per @cliffordwolf | Eddie Hung | 2019-05-03 | 1 | -1/+2 |
| | * | Revert "dffinit -noreinit to silently continue when init value is 1'bx" | Eddie Hung | 2019-05-03 | 1 | -12/+4 |
| | * | synth_xilinx to call dffinit with -noreinit | Eddie Hung | 2019-05-02 | 1 | -1/+1 |
| | * | dffinit -noreinit to silently continue when init value is 1'bx | Eddie Hung | 2019-05-02 | 1 | -4/+12 |
| * | | Merge pull request #976 from YosysHQ/clifford/fix974 | Clifford Wolf | 2019-05-03 | 3 | -0/+25 |
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| | * | | Add splitcmplxassign test case and silence splitcmplxassign warning | Clifford Wolf | 2019-05-01 | 2 | -0/+23 |
| | * | | Fix width detection of memory access with bit slice, fixes #974 | Clifford Wolf | 2019-05-01 | 1 | -0/+2 |
| * | | | Merge pull request #985 from YosysHQ/clifford/fix981 | Clifford Wolf | 2019-05-03 | 2 | -44/+81 |
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| | * | | | Improve opt_expr and opt_clean handling of (partially) undriven and/or unused... | Clifford Wolf | 2019-05-03 | 2 | -44/+81 |
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| * | | | Fix typo in tests/svinterfaces/runone.sh | Clifford Wolf | 2019-05-03 | 1 | -2/+2 |
| * | | | Merge pull request #979 from jakobwenzel/svinterfacesTestcase | Clifford Wolf | 2019-05-03 | 1 | -2/+2 |
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| | * | | fail svinterfaces testcases on yosys error exit | Jakob Wenzel | 2019-05-02 | 1 | -2/+2 |
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| * | | Merge pull request #963 from YosysHQ/eddie/synth_xilinx_fine | Clifford Wolf | 2019-05-02 | 3 | -34/+30 |
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| | * | | Back to passing all xc7srl tests! | Eddie Hung | 2019-05-01 | 1 | -5/+4 |
| | * | | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fine | Eddie Hung | 2019-05-01 | 22 | -190/+286 |
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| | * | | | WIP | Eddie Hung | 2019-04-28 | 1 | -36/+22 |
| | * | | | Move neg-pol to pos-pol mapping from ff_map to cells_map.v | Eddie Hung | 2019-04-28 | 2 | -9/+12 |
| | * | | | Revert synth_xilinx 'fine' label more to how it used to be... | Eddie Hung | 2019-04-26 | 1 | -21/+40 |
| * | | | | Merge pull request #978 from ucb-bar/fmtfirrtl | Eddie Hung | 2019-05-01 | 1 | -25/+25 |
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| | * | | | Re-indent firrtl.cc:struct memory - no functional change. | Jim Lawson | 2019-05-01 | 1 | -25/+25 |
| * | | | | Merge branch 'master' of github.com:YosysHQ/yosys | Eddie Hung | 2019-05-01 | 21 | -176/+273 |
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| | * | | | Merge branch 'clifford/fix883' | Clifford Wolf | 2019-05-02 | 1 | -0/+1 |
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| | | * | | | Add missing enable_undef to "sat -tempinduct-def", fixes #883 | Clifford Wolf | 2019-05-02 | 1 | -0/+1 |
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| | * | | | Merge pull request #977 from ucb-bar/fixfirrtlmem | Clifford Wolf | 2019-05-01 | 3 | -4/+64 |
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| | | * | | | Fix #938 - Crash occurs in case when use write_firrtl command | Jim Lawson | 2019-05-01 | 3 | -4/+64 |
| | * | | | | Fix floating point exception in qwp, fixes #923 | Clifford Wolf | 2019-05-01 | 1 | -1/+1 |
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| | * | | | Fix segfault in wreduce | Clifford Wolf | 2019-04-30 | 1 | -0/+2 |
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| | * | | Disabled "final loop assignment" feature | Clifford Wolf | 2019-04-30 | 1 | -0/+2 |
| | * | | Merge pull request #972 from YosysHQ/clifford/fix968 | Clifford Wolf | 2019-04-30 | 1 | -0/+7 |
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| | | * | | Add final loop variable assignment when unrolling for-loops, fixes #968 | Clifford Wolf | 2019-04-30 | 1 | -0/+7 |
| | * | | | Merge pull request #966 from YosysHQ/clifford/fix956 | Clifford Wolf | 2019-04-30 | 3 | -3/+55 |
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| | | * | | | Add handling of init attributes in "opt_expr -undriven" | Clifford Wolf | 2019-04-30 | 2 | -3/+42 |
| | | * | | | Drive dangling wires with init attr with their init value, fixes #956 | Clifford Wolf | 2019-04-29 | 1 | -0/+13 |
| | * | | | | Merge pull request #962 from YosysHQ/eddie/refactor_synth_xilinx | Clifford Wolf | 2019-04-30 | 2 | -156/+101 |
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| | | * \ \ \ | Merge branch 'master' into eddie/refactor_synth_xilinx | Clifford Wolf | 2019-04-30 | 9 | -12/+40 |
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| | * | | | | | Merge pull request #973 from christian-krieg/feature/python_bindings | Clifford Wolf | 2019-04-30 | 3 | -4/+4 |
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| | | * \ \ \ \ | Merge branch 'master' of https://github.com/YosysHQ/yosys into feature/python... | Benedikt Tutzer | 2019-04-30 | 88 | -320/+2797 |
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| | | * | | | | | Cleaned up root directory | Benedikt Tutzer | 2019-04-30 | 3 | -4/+4 |
| | * | | | | | | Include filename in "Executing Verilog-2005 frontend" message, fixes #959 | Clifford Wolf | 2019-04-30 | 1 | -2/+2 |
| | * | | | | | | Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970 | Clifford Wolf | 2019-04-30 | 1 | -1/+1 |
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| | * | | | | | Merge pull request #960 from YosysHQ/eddie/equiv_opt_undef | Clifford Wolf | 2019-04-29 | 1 | -3/+16 |
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| | | * | | | | | Add -undef option to equiv_opt, passed to equiv_induct | Eddie Hung | 2019-04-26 | 1 | -3/+16 |
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| | * | | | | | Merge pull request #967 from olegendo/depfile_esc_spaces | Clifford Wolf | 2019-04-29 | 3 | -2/+17 |
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| | | * | | | | fix codestyle formatting | Oleg Endo | 2019-04-29 | 3 | -14/+14 |
