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| | * | | | synth_xilinx to call commands of synth -coarse directlyEddie Hung2019-07-091-3/+20
| | * | | | Revert "synth_xilinx to call "synth -run coarse" with "-keepdc""Eddie Hung2019-07-091-2/+2
| | * | | | Fix spacingEddie Hung2019-07-091-1/+1
| | * | | | Fix spacingEddie Hung2019-07-091-1/+1
| | * | | | Decompose mux inputs in delay-orientated (rather than area) fashionEddie Hung2019-07-081-18/+30
| | * | | | Do not call opt -mux_undef (part of -full) before muxcoverEddie Hung2019-07-081-1/+5
| | * | | | Add one more commentEddie Hung2019-07-081-0/+3
| | * | | | Less thinkingEddie Hung2019-07-081-3/+3
| | * | | | RewordEddie Hung2019-07-081-2/+2
| | * | | | synth_xilinx to call "synth -run coarse" with "-keepdc"Eddie Hung2019-07-081-2/+2
| | * | | | Merge remote-tracking branch 'origin/eddie/synth_keepdc' into xc7muxEddie Hung2019-07-084-8/+25
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| | * | | | | Map $__XILINX_SHIFTX in a more balanced mannerEddie Hung2019-07-081-36/+49
| | * | | | | CapitalisationEddie Hung2019-07-081-1/+1
| | * | | | | Add synth_xilinx -widemux recommended valueEddie Hung2019-07-081-1/+1
| | * | | | | Fixes for 2:1 muxesEddie Hung2019-07-082-5/+30
| | * | | | | synth_xilinx -widemux=2 is minimum nowEddie Hung2019-07-081-4/+7
| | * | | | | Parametric muxcover costs as per @daveshah1Eddie Hung2019-07-081-16/+14
| | * | | | | Merge remote-tracking branch 'origin/eddie/muxcover_mux2' into xc7muxEddie Hung2019-07-081-5/+11
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| | * | | | | | atoi -> stoi as per @daveshah1Eddie Hung2019-07-081-1/+1
| | * | | | | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-07-088-90/+60
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| * | \ \ \ \ \ \ Merge pull request #1177 from YosysHQ/clifford/asyncClifford Wolf2019-07-105-8/+135
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| | * | | | | | | Fix tests/various/async FFL testClifford Wolf2019-07-092-1/+8
| | * | | | | | | Improve tests/various/async, disable failing ffl testClifford Wolf2019-07-092-7/+38
| | * | | | | | | Add tests/various/async.{sh,v}Clifford Wolf2019-07-092-0/+88
| | * | | | | | | Improve tests/various/run-test.shClifford Wolf2019-07-091-8/+6
| | * | | | | | | Add tests/simple_abc9/.gitignoreClifford Wolf2019-07-091-0/+3
| * | | | | | | | synth_ecp5: Fix typo in copyright headerDavid Shah2019-07-091-1/+1
| * | | | | | | | Merge pull request #1174 from YosysHQ/eddie/fix1173Clifford Wolf2019-07-091-0/+3
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| | * | | | | | | Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zeroEddie Hung2019-07-091-0/+3
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| * | | | | | | Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-positionClifford Wolf2019-07-091-3/+2
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| | * | | | | | | write_verilog: fix placement of case attributes. NFC.whitequark2019-07-091-3/+2
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| * | | | | | | Merge pull request #1171 from YosysHQ/revert-1166-eddie/synth_keepdcEddie Hung2019-07-093-15/+3
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| | * | | | | | Revert "Add "synth -keepdc" option"Eddie Hung2019-07-093-15/+3
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| * | | | | | Merge pull request #1170 from YosysHQ/eddie/fix_double_underscoreEddie Hung2019-07-091-4/+6
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| | * | | | | Rename __builtin_bswap32 -> bswap32Eddie Hung2019-07-091-4/+6
| * | | | | | Merge pull request #1168 from whitequark/bugpoint-processesClifford Wolf2019-07-092-17/+105
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| | * | | | | | bugpoint: add -assigns and -updates options.whitequark2019-07-091-9/+81
| | * | | | | | proc_clean: add -quiet option.whitequark2019-07-091-8/+24
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| * | | | | | Merge pull request #1169 from whitequark/more-proc-cleanupsClifford Wolf2019-07-095-22/+168
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| | * | | | | | proc_prune: promote assigns to module connections when legal.whitequark2019-07-093-33/+42
| | * | | | | | proc_prune: new pass.whitequark2019-07-093-1/+138
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| * | | | | | Merge pull request #1163 from whitequark/more-case-attrsClifford Wolf2019-07-093-16/+28
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| | * | | | | | verilog_backend: dump attributes on SwitchRule.whitequark2019-07-081-0/+1
| | * | | | | | proc_mux: consider \src attribute on CaseRule.whitequark2019-07-081-10/+16
| | * | | | | | verilog_backend: dump attributes on CaseRule, as comments.whitequark2019-07-081-6/+10
| | * | | | | | genrtlil: emit \src attribute on CaseRule.whitequark2019-07-081-0/+1
| * | | | | | | Merge pull request #1162 from whitequark/rtlil-case-attrsClifford Wolf2019-07-093-5/+15
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| | * | | | | | Allow attributes on individual switch cases in RTLIL.whitequark2019-07-083-5/+15
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| * | | | | | Merge pull request #1167 from YosysHQ/eddie/xc7srl_cleanupClifford Wolf2019-07-091-19/+25
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| | * \ \ \ \ \ Merge branch 'eddie/script_from_wire' into eddie/xc7srl_cleanupEddie Hung2019-07-026-15/+20
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