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* Gowin: deal with active-low tristate (#2971)Pepijn de Vos2021-08-205-7/+15
* Merge pull request #2973 from YosysHQ/micko/optional_extensionsMiodrag Milanović2021-08-202-2/+12
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| * Make Verific extensions optionalMiodrag Milanovic2021-08-202-2/+12
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* Bump versiongithub-actions[bot]2021-08-181-1/+1
* ice40: Fix typo in SB_CARRY specify for LP/UltraPlusSylvain Munaut2021-08-171-2/+2
* Bump versiongithub-actions[bot]2021-08-171-1/+1
* kernel/mem: Remove old parameter when upgrading $mem to $mem_v2.Marcelina Kościelnicka2021-08-161-0/+1
* Bump versiongithub-actions[bot]2021-08-151-1/+1
* proc_prune: Make assign removal and promotion per-bit, remember promoted bits.Marcelina Kościelnicka2021-08-142-40/+47
* Bump versiongithub-actions[bot]2021-08-141-1/+1
* Generate an RTLIL representation of bind constructsRupert Swarbrick2021-08-1311-3/+312
* Add opt_mem_widen pass.Marcelina Kościelnicka2021-08-144-0/+146
* memory_share: Add -nosat and -nowiden options.Marcelina Kościelnicka2021-08-1411-11/+269
* memory_dff: Recognize soft transparency logic.Marcelina Kościelnicka2021-08-134-7/+1355
* Add new opt_mem_priority pass.Marcelina Kościelnicka2021-08-134-2/+319
* Merge pull request #2932 from YosysHQ/mwk/logger-check-expectedMiodrag Milanović2021-08-132-5/+14
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| * logger: Add -check-expected subcommand.Marcelina Kościelnicka2021-08-122-5/+14
* | sv: improve support for wire and var with user-defined typesBrett Witherspoon2021-08-123-11/+152
* | Bump versiongithub-actions[bot]2021-08-131-1/+1
* | memory_share: Pass addresses through sigmap_xmux everywhere.Marcelina Kościelnicka2021-08-131-20/+25
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* Bump versiongithub-actions[bot]2021-08-121-1/+1
* test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer.Marcelina Kościelnicka2021-08-112-78/+156
* memory_dff: Recognize read ports with reset / initial value.Marcelina Kościelnicka2021-08-114-8/+55
* proc_memwr: Use the v2 memwr cell.Marcelina Kościelnicka2021-08-113-14/+24
* Add v2 memory cells.Marcelina Kościelnicka2021-08-1122-206/+631
* Bump versiongithub-actions[bot]2021-08-111-1/+1
* kernel/mem: Introduce transparency masks.Marcelina Kościelnicka2021-08-118-118/+408
* Allow optional comma after last entry in enumMichael Singer2021-08-091-11/+12
* Bump versiongithub-actions[bot]2021-08-101-1/+1
* Refactor common parts of SAT-using optimizations into a helper.Marcelina Kościelnicka2021-08-097-153/+224
* Bump versiongithub-actions[bot]2021-08-081-1/+1
* opt_merge: Use FfInitVals.Marcelina Kościelnicka2021-08-083-28/+51
* Bump versiongithub-actions[bot]2021-08-071-1/+1
* verilog: Support tri/triand/trior wire types.Marcelina Kościelnicka2021-08-061-0/+3
* Bump versiongithub-actions[bot]2021-08-051-1/+1
* memory_share: Don't skip ports with EN wired to input for SAT sharing.Marcelina Kościelnicka2021-08-041-3/+1
* Bump versiongithub-actions[bot]2021-08-041-1/+1
* memory_bram: Move init data swizzling before other swizzling.Marcelina Kościelnicka2021-08-031-18/+18
* Bump versiongithub-actions[bot]2021-08-031-1/+1
* Require latest verificMiodrag Milanovic2021-08-021-1/+1
* Bump versiongithub-actions[bot]2021-08-021-1/+1
* backend/verilog: Add alternate mode for transparent read port output.Marcelina Kościelnicka2021-08-011-1/+71
* memory_bram: Some refactoringMarcelina Kościelnicka2021-08-011-196/+174
* Bump versiongithub-actions[bot]2021-07-311-1/+1
* Update version.ymlMiodrag Milanović2021-07-301-2/+5
* Fixes xc7 BRAM36sMaciej Dudek2021-07-301-4/+6
* proc_rmdead: use explicit pattern set when there are no wildcardsZachary Snow2021-07-294-2/+386
* genrtlil: add width detection for AST_PREFIX nodesZachary Snow2021-07-292-0/+26
* Bump versiongithub-actions[bot]2021-07-301-1/+1
* opt_lut: Allow more than one -dlogic per cell type.Marcelina Kościelnicka2021-07-293-24/+55