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* Added dffsr support to proc_dff passClifford Wolf2013-10-181-7/+72
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* Added RTLIL NEW_WIRE macroClifford Wolf2013-10-182-0/+13
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* Bugfix in dffsr techmap rulesClifford Wolf2013-10-181-8/+8
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* Added techmap rules for $sr, $dffsr and $dlatchClifford Wolf2013-10-181-0/+181
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* Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_Clifford Wolf2013-10-183-0/+181
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* Added $sr, $dffsr and $dlatch cell typesClifford Wolf2013-10-183-49/+80
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* Improved way of connecting ports in techmap passClifford Wolf2013-10-171-18/+36
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* Only prefer connected signals iff they have public namesClifford Wolf2013-10-171-5/+6
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* Added -buf, -true and -false options to blif backendClifford Wolf2013-10-171-2/+40
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* Fixed bug in synthesis of memories that are never writtenClifford Wolf2013-10-171-2/+7
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* Avoid re-arranging signals on register outputsClifford Wolf2013-10-171-3/+31
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* Fixed detection of major wires in opt_cleanClifford Wolf2013-10-171-0/+3
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* Added iopadmap passClifford Wolf2013-10-164-2/+167
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* Moved dfflibmap from passes/dfflibmap to passes/techmapClifford Wolf2013-10-166-11/+10
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* Added map, par and bitgen to xlinx7 exampleClifford Wolf2013-10-161-2/+39
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* Fixed parsing or liberty file statements such as 'clocked_on : "(!CLK)";'Clifford Wolf2013-10-161-1/+4
| | | | Patch by Tim Edwards
* Added recommended apt-get commands to READMEClifford Wolf2013-10-111-2/+20
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* Fixed minisat includeClifford Wolf2013-10-111-1/+1
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* Pinned ABC revision to 0f9e5488ced3Clifford Wolf2013-10-031-1/+3
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* Improvements in EDIF backendClifford Wolf2013-09-172-2/+41
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* Added additional options to BLIF backendClifford Wolf2013-09-151-15/+60
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* Added BLIF backendClifford Wolf2013-09-152-0/+245
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* A couple of small fixes in SPICE backendClifford Wolf2013-09-151-6/+18
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* Moved common techlib files to techlibs/commonClifford Wolf2013-09-1513-17/+17
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* Updated manualClifford Wolf2013-09-153-21/+173
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* Added spice testbench to techlibs/cmosClifford Wolf2013-09-145-6/+73
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* Added spice backendClifford Wolf2013-09-146-0/+306
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-09-032-10/+41
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| * Encode large (>32 bits) parameters as hex string in edif backendClifford Wolf2013-08-281-3/+16
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| * Improved edif backendClifford Wolf2013-08-271-8/+18
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| * Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos)Clifford Wolf2013-08-271-2/+10
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* | Added -selected option to various backendsClifford Wolf2013-09-033-9/+58
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* Added simple xilinx7 technology mapping filesClifford Wolf2013-08-224-0/+167
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* More explicit integer output in verilog backendClifford Wolf2013-08-221-2/+2
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* Added correct encoding of identifiers in EDIF backendClifford Wolf2013-08-221-13/+61
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* Added edif backend (still under construction)Clifford Wolf2013-08-222-0/+202
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* Merge pull request #10 from hansiglaser/masterClifford Wolf2013-08-211-0/+2
|\ | | | | fixed Verilog parser filename and line numbering issue with include files
| * fixed Verilog parser filename and line numbering issue with include filesJohann Glaser2013-08-211-0/+2
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* | Some minor documentation fixesClifford Wolf2013-08-212-2/+2
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* | Merge pull request #9 from hansiglaser/masterClifford Wolf2013-08-203-4/+24
|\| | | | | Added support for include directories with the new '-I' argument of the 'read_verilog' command
| * Added support for include directories with the new '-I' argument of theJohann Glaser2013-08-203-4/+24
| | | | | | | | 'read_verilog' command
* | Merge pull request #8 from hansiglaser/masterClifford Wolf2013-08-202-4/+8
|\| | | | | Added support for notif0/notif1 primitives
| * Added support for notif0/notif1 primitivesJohann Glaser2013-08-202-4/+8
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* Added cleaning of old version_* files to version_* make ruleClifford Wolf2013-08-201-1/+2
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* Added version info to yosys command and added -V optionClifford Wolf2013-08-203-2/+22
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* Minor fixes in abc build instructions and abc passClifford Wolf2013-08-202-5/+5
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* Fixed width and sign detection for ** operatorClifford Wolf2013-08-191-3/+3
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* Added support for bufif0/bufif1 primitivesClifford Wolf2013-08-192-33/+59
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* Improved ast dumping (ast/verilog frontend)Clifford Wolf2013-08-194-64/+35
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* Implemented same div-by-zero behavior as found in other synthesis toolsClifford Wolf2013-08-152-7/+59
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