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Age
Files
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Optimize ceil_log2 function
Matthew Daiter
2019-05-07
2
-3
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+5
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Merge pull request #946 from YosysHQ/clifford/specify
Clifford Wolf
2019-05-06
19
-51
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+810
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Improve tests/various/specify.ys
Clifford Wolf
2019-05-06
1
-2
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+32
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Add "real" keyword to ilang format
Clifford Wolf
2019-05-06
3
-2
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+12
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Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify
Clifford Wolf
2019-05-06
3
-12
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+32
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Improve write_verilog specify support
Clifford Wolf
2019-05-04
3
-16
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+75
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Update README
Clifford Wolf
2019-05-04
1
-5
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+1
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More testing
Eddie Hung
2019-05-03
2
-2
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+5
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Fix spacing
Eddie Hung
2019-05-03
1
-6
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+6
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Add quick-and-dirty specify tests
Eddie Hung
2019-05-03
2
-0
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+53
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Merge remote-tracking branch 'origin/master' into clifford/specify
Eddie Hung
2019-05-03
40
-405
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+931
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Add specify support to README
Clifford Wolf
2019-04-23
1
-0
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+5
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Improve $specrule interface
Clifford Wolf
2019-04-23
4
-13
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+23
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Improve $specrule interface
Clifford Wolf
2019-04-23
3
-24
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+24
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Add $specrule cells for $setup/$hold/$skew specify rules
Clifford Wolf
2019-04-23
9
-6
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+133
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Preserve $specify[23] cells
Clifford Wolf
2019-04-23
1
-1
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+1
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Allow $specify[23] cells in blackbox modules
Clifford Wolf
2019-04-23
1
-0
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+6
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Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom...
Clifford Wolf
2019-04-23
4
-76
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+76
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Add $specify2/$specify3 support to write_verilog
Clifford Wolf
2019-04-23
1
-0
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+47
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Add support for $assert/$assume/$cover to write_verilog
Clifford Wolf
2019-04-23
1
-0
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+10
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Add CellTypes support for $specify2 and $specify3
Clifford Wolf
2019-04-23
2
-0
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+7
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Add InternalCellChecker support for $specify2 and $specify3
Clifford Wolf
2019-04-23
1
-7
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+21
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Checking and fixing specify cells in genRTLIL
Clifford Wolf
2019-04-23
1
-1
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+15
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Un-break default specify parser
Clifford Wolf
2019-04-23
1
-0
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+1
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Add specify parser
Clifford Wolf
2019-04-23
5
-33
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+253
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Add $specify2 and $specify3 cells to simlib
Clifford Wolf
2019-04-23
1
-0
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+147
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Merge pull request #975 from YosysHQ/clifford/fix968
Clifford Wolf
2019-05-06
3
-13
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+66
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Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968
Clifford Wolf
2019-05-06
35
-290
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+787
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Further improve unused-detection for opt_clean driver-driver conflict warning
Clifford Wolf
2019-05-03
1
-5
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+8
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Improve unused-detection for opt_clean driver-driver conflict warning
Clifford Wolf
2019-05-03
1
-21
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+29
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Add additional test cases for for-loops
Clifford Wolf
2019-05-01
1
-0
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+25
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Silently resolve completely unused cell-vs-const driver-driver conflicts
Clifford Wolf
2019-05-01
1
-2
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+21
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Re-enable "final loop assignment" feature
Clifford Wolf
2019-05-01
1
-2
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+0
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Merge pull request #871 from YosysHQ/verific_import
Clifford Wolf
2019-05-06
4
-44
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+181
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Add tests/various/chparam.sh
Clifford Wolf
2019-05-06
1
-0
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+52
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Add "hierarchy -chparam" support for non-verific top modules
Clifford Wolf
2019-05-03
1
-12
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+35
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log_warning_noprefix -> log_warning as per review
Eddie Hung
2019-05-03
1
-1
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+1
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For hier_tree::Elaborate() also include SV root modules (bind)
Eddie Hung
2019-05-03
1
-23
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+36
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Fix verific_parameters construction, use attribute to mark top netlists
Eddie Hung
2019-05-03
2
-8
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+12
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WIP -chparam support for hierarchy when verific
Eddie Hung
2019-05-03
3
-19
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+41
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verific_import() changes to avoid ElaborateAll()
Eddie Hung
2019-05-03
1
-15
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+38
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Fix the other bison warning in ilang_parser.y
Clifford Wolf
2019-05-06
1
-1
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+1
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Bugfix in peepopt_shiftmul.pmg
Clifford Wolf
2019-05-06
1
-0
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+4
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Merge pull request #992 from bwidawsk/bison-fix
Clifford Wolf
2019-05-06
1
-1
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+1
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verilog_parser: Fix Bison warning
Ben Widawsky
2019-05-05
1
-1
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+1
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Merge pull request #989 from YosysHQ/dave/abc_name_improve
Clifford Wolf
2019-05-06
1
-8
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+21
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abc: Fix handling of postfixed names (e.g. for retiming)
David Shah
2019-05-04
1
-4
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+4
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abc: Improve name recovery
David Shah
2019-05-04
1
-4
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+17
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Fix bug in "expose -input"
Clifford Wolf
2019-05-06
1
-1
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+1
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Cleanups in opt_clean
Clifford Wolf
2019-05-06
1
-47
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+16
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