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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-22 09:26:20 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-04-23 21:36:59 +0200 |
| commit | e1d73e03d38e9408cc7bce685645bb170ca5a6b8 (patch) | |
| tree | 5df12ac7818453f2036622b5c6cc0fe0fba49daa | |
| parent | b232e027bf18bd37206c15209e23d2f8f7b2a17d (diff) | |
| download | yosys-e1d73e03d38e9408cc7bce685645bb170ca5a6b8.tar.gz yosys-e1d73e03d38e9408cc7bce685645bb170ca5a6b8.tar.bz2 yosys-e1d73e03d38e9408cc7bce685645bb170ca5a6b8.zip | |
Add InternalCellChecker support for $specify2 and $specify3
Signed-off-by: Clifford Wolf <clifford@clifford.at>
| -rw-r--r-- | kernel/rtlil.cc | 28 |
1 files changed, 21 insertions, 7 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7d5334eb1..9e06b8323 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1194,13 +1194,27 @@ namespace { return; } - if (cell->type == "$specify2") { - // FIXME - return; - } - - if (cell->type == "$specify3") { - // FIXME + if (cell->type.in("$specify2", "$specify3")) { + param_bool("\\FULL"); + param_bool("\\SRC_DST_PEN"); + param_bool("\\SRC_DST_POL"); + param("\\T_RISE_MIN"); + param("\\T_RISE_AVG"); + param("\\T_RISE_MAX"); + param("\\T_FALL_MIN"); + param("\\T_FALL_AVG"); + param("\\T_FALL_MAX"); + port("\\EN", 1); + port("\\SRC", param("\\SRC_WIDTH")); + port("\\DST", param("\\DST_WIDTH")); + if (cell->type == "$specify3") { + param_bool("\\EDGE_EN"); + param_bool("\\EDGE_POL"); + param_bool("\\DAT_DST_PEN"); + param_bool("\\DAT_DST_POL"); + port("\\DAT", param("\\DST_WIDTH")); + } + check_expected(); return; } |