aboutsummaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
* Removed VOUT port of GP_BANDGAPAndrew Zonenberg2016-07-111-1/+1
* Removed splitnets in prep for new gp4par parserAndrew Zonenberg2016-07-111-1/+0
* Yosys-smtbmc: Support for hierarchical VCD dumpingClifford Wolf2016-07-112-23/+59
* Moved smt2 yosys info parsing from smtbmc.py to smtio.pyClifford Wolf2016-07-113-16/+56
* Added "prep -auto-top" and "synth -auto-top"Clifford Wolf2016-07-112-6/+23
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2016-07-101-0/+26
|\
| * Merge pull request #189 from whitequark/masterClifford Wolf2016-07-101-0/+26
| |\
| | * greenpak4: add GP_COUNT{8,14}_ADV cells.whitequark2016-07-101-0/+26
| |/
* / Support for hierarchical designs in smt2 back-endClifford Wolf2016-07-102-24/+144
|/
* Further improved fsm_detect output, attempt to detect self-resetting circuitsClifford Wolf2016-07-091-6/+68
* Added printing of some warning messages to fsm_detectClifford Wolf2016-07-091-14/+61
* Added warning about adding fsm_encoding attributes to wires to manualClifford Wolf2016-07-081-0/+4
* Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiationsClifford Wolf2016-07-082-13/+24
* Fixed mem assignment in left-hand-side concatenationClifford Wolf2016-07-082-0/+57
* Merge branch 'eddiehung-vtr'Clifford Wolf2016-07-081-9/+17
|\
| * Restored blif "-true - .." behavior, use "-true + .." for eddiehung-vtr behaviorClifford Wolf2016-07-081-13/+15
| * In BLIF, a .names without entries already always outputs 0Clifford Wolf2016-07-081-11/+0
| * Undo eddiehung-vtr Makefile changesClifford Wolf2016-07-081-5/+1
| * Merge branch 'yosys-0.5-vtr' of https://github.com/eddiehung/yosys into eddie...Clifford Wolf2016-07-082-3/+24
|/|
| * Fix for all zero maskeddiehung2015-05-032-1/+16
| * Escape '<' and '>' some moreeddiehung2015-05-031-1/+1
| * For vtr, escape angle brackets as welleddiehung2015-04-281-1/+1
| * blifwriter: write out .names for true/false/undef type == '-'eddiehung2015-04-281-0/+6
* | Fixed autotest.sh handling of `timescaleClifford Wolf2016-07-021-14/+10
* | Merge branch 'assert-limit'Clifford Wolf2016-07-011-9/+33
|\ \
| * | Replaced "select -assert-limit" with -assert-max and -assert-minClifford Wolf2016-07-011-42/+29
| * | Added 'assert-limit' option for 'select' commandeshellko2016-07-011-5/+42
|/ /
* | Improved ice40_ffinit error reportingClifford Wolf2016-06-301-1/+5
* | Merge pull request #181 from rubund/input_logic_allowedClifford Wolf2016-06-211-2/+2
|\ \
| * | Allow defining input ports as "input logic" in SystemVerilogRuben Undheim2016-06-201-2/+2
|/ /
* | Bugfix in "abc -script" handlingClifford Wolf2016-06-191-53/+50
* | Merge branch 'sv_packages' of https://github.com/rubund/yosysClifford Wolf2016-06-197-1/+52
|\ \
| * | A few modifications after pull request commentsRuben Undheim2016-06-183-5/+4
| * | Added support for SystemVerilog packages with localparam definitionsRuben Undheim2016-06-187-1/+53
* | | Added "deminout"Clifford Wolf2016-06-193-0/+118
* | | Added "read_blif -sop"Clifford Wolf2016-06-181-5/+10
* | | Added $sop support to BLIF back-endClifford Wolf2016-06-181-2/+29
|/ /
* | Added "dc2" to default ABC scriptsClifford Wolf2016-06-171-5/+5
* | Fixed init issue in mem2reg_test2 test caseClifford Wolf2016-06-171-2/+6
* | Added "abc -I <num> -P <num>"Clifford Wolf2016-06-171-8/+33
* | Added $sop SAT modelClifford Wolf2016-06-171-0/+82
* | Improved support for $sop cellsClifford Wolf2016-06-176-10/+89
* | Added $sop cell type and "abc -sop"Clifford Wolf2016-06-177-31/+171
* | Updated ABC to hg rev b5df6e2b76f0Clifford Wolf2016-06-172-10/+10
* | Added "nlutmap -assert"Clifford Wolf2016-06-092-3/+17
* | Do not run "wreduce" in "prep -ifx"Clifford Wolf2016-06-081-2/+3
* | Added "proc_mux -ifx"Clifford Wolf2016-06-063-21/+54
* | Added "setundef -init"Clifford Wolf2016-06-031-5/+89
* | Fix all undef-muxes in dlatch input coneClifford Wolf2016-06-021-34/+72
* | Avoid creating undef-muxes when inferring latches in proc_dlatchClifford Wolf2016-06-011-0/+44
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 21:52:14 +0000