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* show: Add -nobg argument.Tim 'mithro' Ansell2020-02-151-6/+13
| | | | Makes yosys wait for the viewer command to finish before continuing.
* Merge pull request #1706 from YosysHQ/mmicko/remove_executable_flagMiodrag Milanović2020-02-155-0/+0
|\ | | | | Remove executable flag from files
| * Remove executable flag from filesMiodrag Milanovic2020-02-155-0/+0
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* Add comment for macOS dependency installMiodrag Milanović2020-02-151-1/+1
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* Revert "abc9: fix abc9_arrival for flops"Eddie Hung2020-02-142-36/+4
| | | | This reverts commit f7c0dbecee7ee8f2e3fc8bc8337e7045fd4aff15.
* Merge pull request #1701 from nakengelhardt/rpc-testMiodrag Milanović2020-02-143-7/+7
|\ | | | | make rpc frontend unix socket test less fragile
| * make rpc frontend unix socket test less fragileN. Engelhardt2020-02-133-7/+7
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* | Merge pull request #1700 from YosysHQ/eddie/abc9_fixesEddie Hung2020-02-133-29/+51
|\ \ | | | | | | Use (* abc9_init *) attribute, fix use of abc9_arrival for flops
| * | write_xaiger: default value for abc9_initEddie Hung2020-02-131-1/+1
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| * | abc9: fix abc9_arrival for flopsEddie Hung2020-02-132-4/+36
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| * | abc9: deprecate abc9_ff.init wire for (* abc9_init *) attrEddie Hung2020-02-132-24/+14
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* | Merge pull request #1699 from YosysHQ/eddie/fix_iopad_initEddie Hung2020-02-132-0/+46
|\ \ | |/ |/| iopadmap: move \init attributes from outpad output to its input
| * Fine tune #1699 testsEddie Hung2020-02-131-14/+14
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| * iopadmap: fixes as suggested by @mwkmwkmwkEddie Hung2020-02-131-19/+11
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| * iopadmap: move \init attributes from outpad output to its inputEddie Hung2020-02-132-3/+57
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* Merge pull request #1694 from rqou/json_compat_fixClaire Wolf2020-02-131-3/+3
|\ | | | | json: Change compat mode to directly emit ints <= 32 bits
| * json: Change compat mode to directly emit ints <= 32 bitsR. Ou2020-02-091-3/+3
| | | | | | | | | | | | This increases compatibility with certain older parsers in some cases that worked before commit 15fae357 but do not work with the current compat-int mode
* | Merge pull request #1679 from thasti/delay-parsingN. Engelhardt2020-02-132-2/+7
|\ \ | | | | | | Fix crash on wire declaration with delay
| * | add testcase for #1614Stefan Biereigel2020-02-031-0/+5
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| * | correct wire declaration grammar for #1614Stefan Biereigel2020-02-031-2/+2
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* | | abc9: cleanupEddie Hung2020-02-102-41/+41
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* | | Merge pull request #1670 from rodrigomelo9/masterEddie Hung2020-02-107-3/+152
|\ \ \ | | | | | | | | $readmem[hb] file inclusion is now relative to the Verilog file
| * | | Added 'set -e' into tests/memfile/run-test.shRodrigo Alejandro Melo2020-02-061-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | Also added two checks for situations where the execution must fail. Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
| * | | Modified $readmem[hb] to use '\' or '/' according the OSRodrigo Alejandro Melo2020-02-061-1/+6
| | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
| * | | Merge branch 'master' into masterRodrigo A. Melo2020-02-0310-4/+367
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| * \ \ \ Merge branch 'master' of https://github.com/YosysHQ/yosysRodrigo Alejandro Melo2020-02-0312-112/+369
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Solved a conflict into the CHANGELOG Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
| * | | | | Replaced strlen by GetSize into simplify.ccRodrigo Alejandro Melo2020-02-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As recommended in CodingReadme. Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
| * | | | | Removed 'synth' into tests/memfile/run-test.shRodrigo Alejandro Melo2020-02-021-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
| * | | | | Added content1.dat into tests/memfileRodrigo Alejandro Melo2020-02-022-21/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modified run-test.sh to use it. Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
| * | | | | Removed a line jump into the CHANGELOGRodrigo Alejandro Melo2020-02-011-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
| * | | | | Added tests/memfile to 'make test' with an extra testcaseRodrigo Alejandro Melo2020-02-012-16/+11
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
| * | | | | Added a test for the Memory Content File inclusion using $readmembRodrigo Alejandro Melo2020-02-013-0/+63
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
| * | | | | Fixed a bug in the new feature of $readmem[hb] when an empty string is providedRodrigo Alejandro Melo2020-02-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
| * | | | | Modified the new search for files of $readmem[hb] to be backward compatibleRodrigo Alejandro Melo2020-01-311-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
| * | | | | $readmem[hb] file inclusion is now relative to the Verilog fileRodrigo Alejandro Melo2020-01-312-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
* | | | | | Merge pull request #1669 from thasti/pyosys-attrsN. Engelhardt2020-02-101-2/+38
|\ \ \ \ \ \ | | | | | | | | | | | | | | Make RTLIL attributes accessible via pyosys
| * | | | | | remove namespace mention from inheritance informationStefan Biereigel2020-02-031-1/+1
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| * | | | | | expose polymorphism through python wrappersStefan Biereigel2020-02-031-2/+8
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| * | | | | | add inheritance for pywrap generatorsStefan Biereigel2020-01-301-0/+30
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* | | | | | Merge pull request #1695 from whitequark/manual-explain-wire-upto-offsetwhitequark2020-02-091-0/+7
|\ \ \ \ \ \ | |_|_|_|_|/ |/| | | | | manual: explain RTLIL::Wire::{upto,offset}
| * | | | | manual: explain RTLIL::Wire::{upto,offset}.whitequark2020-02-091-0/+7
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* | | | | Remove unnecessary commaEddie Hung2020-02-071-3/+2
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* | | | | Merge pull request #1687 from YosysHQ/eddie/fix_ystestsEddie Hung2020-02-072-9/+7
|\ \ \ \ \ | | | | | | | | | | | | Fix shiftx2mux, fix yosys-tests
| * | | | | techmap: fix shiftx2mux decompositionEddie Hung2020-02-071-8/+6
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| * | | | | Fix misc.abc9.abc9_abc9_lutsEddie Hung2020-02-071-1/+1
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* | | | | xilinx: Add support for LUT RAM on LUT4-based devices.Marcin Kościelnicki2020-02-075-27/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are multiple other kinds of RAMs supported on these devices, but RAM16X1D is the only dual-port one. Fixes #1549
* | | | | xilinx: Initial support for LUT4 devices.Marcin Kościelnicki2020-02-076-54/+235
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds support for mapping logic, including LUTs, wide LUTs, and carry chains. Fixes #1547
* | | | | Merge pull request #1685 from dh73/gowinEddie Hung2020-02-061-1/+1
|\ \ \ \ \ | | | | | | | | | | | | Removing cells_sim from GoWin bram techmap
| * | | | | Removing cells_sim.v from bram techmap passDiego H2020-02-061-1/+1
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* | | | | | Merge pull request #1683 from whitequark/write_verilog-memattrswhitequark2020-02-071-0/+1
|\ \ \ \ \ \ | | | | | | | | | | | | | | write_verilog: dump $mem cell attributes
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