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* Check nusers of DSP output, not whole flopEddie Hung2019-08-091-1/+1
* Improve ice40_dsp for non-fully-32-bit addersEddie Hung2019-08-091-3/+8
* Add wreduce to synth_ice40 -dsp as wellEddie Hung2019-08-091-0/+1
* Another filter -> ifEddie Hung2019-08-091-2/+2
* CleanupEddie Hung2019-08-092-18/+18
* Pack partial-product adder DSP48E1 packingEddie Hung2019-08-093-10/+81
* Fix checkEddie Hung2019-08-091-4/+6
* Revert "Fix typo"Eddie Hung2019-08-091-1/+1
* Remove muxY and ffY for nowEddie Hung2019-08-082-35/+33
* Remove signed from ports in +/xilinx/dsp_map.vEddie Hung2019-08-081-1/+1
* Rework ice40_dsp to map to SB_MAC16 earlier, and check before packingEddie Hung2019-08-086-40/+119
* Combine techmap callsEddie Hung2019-08-081-2/+1
* Only pack registers if {A,B,P}REG = 0, do not pack $dffeEddie Hung2019-08-081-3/+6
* Move xilinx_dsp to before alumaccEddie Hung2019-08-081-6/+4
* Disable $dffeEddie Hung2019-08-081-8/+8
* INMODE is 5 bitsEddie Hung2019-08-081-1/+1
* Fix copy-pasta typoEddie Hung2019-08-081-2/+2
* ecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinxDavid Shah2019-08-081-11/+11
* ecp5: Bring up to date with mul2dsp changesDavid Shah2019-08-082-2/+10
* Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspDavid Shah2019-08-0852-562/+1165
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| * Fix compile errorEddie Hung2019-08-071-2/+2
| * Run "opt_expr -fine" instead of "wreduce" due to #1213Eddie Hung2019-08-071-2/+1
| * Do not SigSpec::extract() beyond boundsEddie Hung2019-08-072-8/+10
| * Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-0749-552/+1134
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| | * Merge pull request #1248 from YosysHQ/eddie/abc9_speedupEddie Hung2019-08-074-40/+48
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| | | * Add commentEddie Hung2019-08-071-2/+3
| | | * Revert "Add TODO"Eddie Hung2019-08-071-2/+0
| | | * Add TODOEddie Hung2019-08-071-0/+2
| | | * Compute box_lookup just onceEddie Hung2019-08-071-8/+24
| | | * Run "clean" on mapped_mod in its own designEddie Hung2019-08-072-24/+10
| | | * Run "clean -purge" on holes_module in its own designEddie Hung2019-08-071-6/+11
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| | * Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixesDavid Shah2019-08-071-101/+244
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| | | * ecp5: Make cells_sim.v consistent with nextpnrDavid Shah2019-08-071-101/+244
| | * | Merge pull request #1213 from YosysHQ/eddie/wreduce_addClifford Wolf2019-08-075-3/+226
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| | | * | Add signed opt_expr testsEddie Hung2019-08-061-0/+50
| | | * | Add signed testEddie Hung2019-08-061-0/+26
| | | * | Move LSB-trimming functionality from wreduce to opt_exprEddie Hung2019-08-062-23/+26
| | | * | Add SigSpec::extract_end() convenience functionEddie Hung2019-08-061-0/+1
| | | * | Restore original SigSpec::extract()Eddie Hung2019-08-061-1/+1
| | | * | Move LSB tests from wreduce to opt_exprEddie Hung2019-08-062-99/+101
| | | * | Merge remote-tracking branch 'origin/master' into eddie/wreduce_addEddie Hung2019-08-0656-172/+763
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| | | * | | Try and fix againEddie Hung2019-07-191-5/+4
| | * | | | Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnorClifford Wolf2019-08-072-94/+206
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| | | * | | | Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog...Jim Lawson2019-07-312-94/+206
| | | * | | | Merge remote-tracking branch 'upstream/master'Jim Lawson2019-07-3021-32/+164
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| | | * \ \ \ \ Merge remote-tracking branch 'upstream/master'Jim Lawson2019-07-24199-1214/+9423
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| | * | \ \ \ \ \ Merge pull request #1249 from mmicko/anlogic_fixClifford Wolf2019-08-071-16/+8
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| | | * | | | | | | anlogic : Fix alu mappingMiodrag Milanovic2019-08-031-16/+8
| | * | | | | | | | Merge pull request #1252 from YosysHQ/clifford/fix1231Clifford Wolf2019-08-071-15/+2
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| | | * | | | | | | | Fix handling of functions/tasks without top-level begin-end block, fixes #1231Clifford Wolf2019-08-061-15/+2
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