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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-08 10:44:49 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-08 10:44:49 -0700 |
| commit | 911129e3ef9196a2f775d97746d704ed761da40d (patch) | |
| tree | 061b2c4c477328f100476a87f86793f63e26beab | |
| parent | 57b2e4b9c1dda6d092e261f90a311087c62d0bc4 (diff) | |
| download | yosys-911129e3ef9196a2f775d97746d704ed761da40d.tar.gz yosys-911129e3ef9196a2f775d97746d704ed761da40d.tar.bz2 yosys-911129e3ef9196a2f775d97746d704ed761da40d.zip | |
Disable $dffe
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index be510b4cb..74bcbf451 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -58,11 +58,11 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm) SigSpec Q = st.ffA->getPort("\\Q"); A.replace(Q, D); cell->setPort("\\A", A); - cell->setParam("\\AREG", State::S1); + cell->setParam("\\AREG", 1); if (st.ffA->type == "$dff") cell->setPort("\\CEA2", State::S1); - else if (st.ffA->type == "$dffe") - cell->setPort("\\CEA2", st.ffA->getPort("\\EN")); + //else if (st.ffA->type == "$dffe") + // cell->setPort("\\CEA2", st.ffA->getPort("\\EN")); else log_abort(); } if (st.ffB) { @@ -71,11 +71,11 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm) SigSpec Q = st.ffB->getPort("\\Q"); B.replace(Q, D); cell->setPort("\\B", B); - cell->setParam("\\BREG", State::S1); + cell->setParam("\\BREG", 1); if (st.ffB->type == "$dff") cell->setPort("\\CEB2", State::S1); - else if (st.ffB->type == "$dffe") - cell->setPort("\\CEB2", st.ffB->getPort("\\EN")); + //else if (st.ffB->type == "$dffe") + // cell->setPort("\\CEB2", st.ffB->getPort("\\EN")); else log_abort(); } if (st.ffP) { @@ -91,8 +91,8 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm) cell->setParam("\\PREG", State::S1); if (st.ffP->type == "$dff") cell->setPort("\\CEP", State::S1); - else if (st.ffP->type == "$dffe") - cell->setPort("\\CEP", st.ffP->getPort("\\EN")); + //else if (st.ffP->type == "$dffe") + // cell->setPort("\\CEP", st.ffP->getPort("\\EN")); else log_abort(); st.ffP->connections_.at("\\Q").replace(P, pm.module->addWire(NEW_ID, GetSize(P))); |