iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Fix warning	Eddie Hung	2019-05-21	1	-3/+2
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* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge pull request #1017 from Kmanfi/bigger_verilog_files	Clifford Wolf	2019-05-18	1	-1/+1
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\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Read bigger Verilog files.	Kaj Tuomi	2019-05-18	1	-1/+1
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* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge pull request #1013 from antmicro/parameter_attributes	Clifford Wolf	2019-05-16	3	-2/+24
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\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Added tests for Verilog frontent for attributes on parameters and localparams	Maciej Kurc	2019-05-16	2	-0/+22
\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Added support for parsing attributes on parameters in Verilog frontent. Conte...	Maciej Kurc	2019-05-16	1	-2/+2
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge pull request #1012 from YosysHQ/clifford/sigspecrw	Clifford Wolf	2019-05-15	3	-17/+92
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\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Improvements in opt_clean	Clifford Wolf	2019-05-15	1	-10/+10
\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Add rewrite_sigspecs2, Improve remove() wires	Clifford Wolf	2019-05-15	2	-7/+82
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* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Do not leak file descriptors in cover.cc	Clifford Wolf	2019-05-15	1	-5/+6
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge pull request #1011 from hzeller/fix-constructing-string-from-int	Clifford Wolf	2019-05-15	2	-2/+3
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\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Fix two instances of integer-assignment to string.	Henner Zeller	2019-05-14	2	-2/+3
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge pull request #1010 from hzeller/yacc-self-contained	Clifford Wolf	2019-05-15	2	-2/+18
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\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Make the generated *.tab.hh include all the headers needed to define the union.	Henner Zeller	2019-05-14	2	-2/+18
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* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge pull request #1008 from thasti/fix_libyosys_build	Clifford Wolf	2019-05-15	1	-5/+6
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\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	extract python prefix to allow overriding	Stefan Biereigel	2019-05-14	1	-1/+2
\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	remove ldconfig call	Stefan Biereigel	2019-05-14	1	-1/+0
\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	add mkdir for libyosys target, explicitly copy to target folder	Stefan Biereigel	2019-05-14	1	-3/+4
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* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge pull request #1005 from smunaut/ice40_hfosc_trim	David Shah	2019-05-15	1	-0/+11
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\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC	Sylvain Munaut	2019-05-13	1	-0/+11
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	bugpoint: check for -script option.	whitequark	2019-05-14	1	-0/+3
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* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge pull request #1004 from YosysHQ/clifford/fix1002	Clifford Wolf	2019-05-12	1	-3/+11
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\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Fix handling of glob_abort_cnt in opt_muxtree, fixes #1002	Clifford Wolf	2019-05-12	1	-3/+11
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* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge pull request #1003 from makaimann/zinit-all	Clifford Wolf	2019-05-11	1	-1/+1
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\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Zinit option '-singleton' -> '-all'	Makai Mann	2019-05-10	1	-1/+1
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Add "fmcombine -initeq -anyeq"	Clifford Wolf	2019-05-11	1	-3/+38
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Add "stat -tech xilinx"	Clifford Wolf	2019-05-11	2	-4/+74
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* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge pull request #1000 from bwidawsk/synth-format	Clifford Wolf	2019-05-09	2	-222/+224
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\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Fix formatting for synth_intel.cc	Ben Widawsky	2019-05-09	1	-222/+211
\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Add a .clang-format	Ben Widawsky	2019-05-09	1	-0/+13
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* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Add $stop to documentation	Clifford Wolf	2019-05-09	1	-3/+4
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Remove added newline (by re-running minisat 00_UPDATE.sh)	Clifford Wolf	2019-05-08	1	-1/+0
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge pull request #991 from kristofferkoch/gcc9-warnings	Clifford Wolf	2019-05-08	5	-5/+9
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\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Fix all warnings that occurred when compiling with gcc9	Kristoffer Ellersgaard Koch	2019-05-08	5	-5/+9
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge pull request #998 from mdaiter/get_bool_attribute_opts	Clifford Wolf	2019-05-08	1	-4/+8
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\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Minor optimization to get_attribute_bool	Matthew Daiter	2019-05-07	1	-4/+8
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Add test case from #997	Clifford Wolf	2019-05-07	1	-0/+12
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Fix handling of partial init attributes in write_verilog, fixes #997	Clifford Wolf	2019-05-07	1	-1/+2
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge pull request #996 from mdaiter/ceil_log2_opts	Clifford Wolf	2019-05-07	2	-3/+5
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\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Optimize ceil_log2 function	Matthew Daiter	2019-05-07	2	-3/+5
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* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Add "synth_xilinx -arch"	Clifford Wolf	2019-05-07	1	-1/+13
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	More opt_clean cleanups	Clifford Wolf	2019-05-07	1	-26/+36
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* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge pull request #946 from YosysHQ/clifford/specify	Clifford Wolf	2019-05-06	19	-51/+810
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\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Improve tests/various/specify.ys	Clifford Wolf	2019-05-06	1	-2/+32
\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Add "real" keyword to ilang format	Clifford Wolf	2019-05-06	3	-2/+12
\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify	Clifford Wolf	2019-05-06	3	-12/+32
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\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Improve write_verilog specify support	Clifford Wolf	2019-05-04	3	-16/+75
\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Update README	Clifford Wolf	2019-05-04	1	-5/+1
\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	More testing	Eddie Hung	2019-05-03	2	-2/+5
\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Fix spacing	Eddie Hung	2019-05-03	1	-6/+6