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| author | Clifford Wolf <clifford@clifford.at> | 2017-04-05 11:25:22 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-04-05 11:25:22 +0200 |
| commit | fcb274a5644016c4090cdfbfbd795f311a7e58f5 (patch) | |
| tree | 863dc8885d85c748ff5114279af77394cc55fe36 | |
| parent | dee4ec1661a2c2d7d6a4a47f7da922b870bbace8 (diff) | |
| download | yosys-fcb274a5644016c4090cdfbfbd795f311a7e58f5.tar.gz yosys-fcb274a5644016c4090cdfbfbd795f311a7e58f5.tar.bz2 yosys-fcb274a5644016c4090cdfbfbd795f311a7e58f5.zip | |
Add ConstEval defaultval feature
| -rw-r--r-- | kernel/consteval.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/kernel/consteval.h b/kernel/consteval.h index 4d48b45ea..0229f5045 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -36,8 +36,9 @@ struct ConstEval SigSet<RTLIL::Cell*> sig2driver; std::set<RTLIL::Cell*> busy; std::vector<SigMap> stack; + RTLIL::State defaultval; - ConstEval(RTLIL::Module *module) : module(module), assign_map(module) + ConstEval(RTLIL::Module *module, RTLIL::State defaultval = RTLIL::State::Sm) : module(module), assign_map(module), defaultval(defaultval) { CellTypes ct; ct.setup_internals(); @@ -365,6 +366,12 @@ struct ConstEval if (sig.is_fully_const()) return true; + if (defaultval != RTLIL::State::Sm) { + for (auto &bit : sig) + if (bit.wire) bit = defaultval; + return true; + } + for (auto &c : sig.chunks()) if (c.wire != NULL) undef.append(c); |