iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fixed O(n^2) performance bug in verilog preprocessor	Clifford Wolf	2013-11-22	1	-1/+1
*	Added more performance measurement infrastructure	Clifford Wolf	2013-11-22	2	-2/+43
*	Enable {* .. *} feature per default (removes dependency to REJECT feature in ...	Clifford Wolf	2013-11-22	5	-24/+3
*	Massive performance improvement from refactoring RTLIL::SigSpec::optimize()	Clifford Wolf	2013-11-22	1	-30/+13
*	Added SigBit struct and refactored RTLIL::SigSpec::extract	Clifford Wolf	2013-11-22	2	-24/+119
*	Improved make rules for profiling and debugging	Clifford Wolf	2013-11-22	1	-3/+3
*	Updated abc	Clifford Wolf	2013-11-21	4	-11/+39
*	Implemented $_DFFSR_ expression generator in verilog backend	Clifford Wolf	2013-11-21	1	-1/+44
*	Fixed async proc detection in mem2reg	Clifford Wolf	2013-11-21	1	-5/+9
*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21	10	-89/+375
*	Fixed a bug in "add -global_input"	Clifford Wolf	2013-11-21	1	-16/+17
*	Added "proc_arst -global_arst" feature	Clifford Wolf	2013-11-20	2	-8/+81
*	Fixed ilang parser: memory width	Clifford Wolf	2013-11-20	1	-1/+1
*	Added "add" command (only wires for now)	Clifford Wolf	2013-11-20	2	-0/+155
*	Another name resolution bugfix for generate blocks	Clifford Wolf	2013-11-20	2	-4/+61
*	Implemented indexed part selects	Clifford Wolf	2013-11-20	4	-3/+19
*	Do not allow memory bit select on the left side of an assignment	Clifford Wolf	2013-11-20	1	-1/+1
*	Added "synthesis" in (synopsys\|synthesis) comment support	Clifford Wolf	2013-11-20	1	-6/+6
*	Fixed name resolution of local tasks and functions in generate block	Clifford Wolf	2013-11-20	2	-3/+16
*	Implemented part/bit select on memory read	Clifford Wolf	2013-11-20	4	-5/+104
*	Updated TODOs in README file	Clifford Wolf	2013-11-20	1	-6/+26
*	Added init= attribute for fpga-style reset values	Clifford Wolf	2013-11-20	2	-6/+23
*	Added "make config-sudo"	Clifford Wolf	2013-11-19	1	-6/+10
*	Install simlib in datdir	Clifford Wolf	2013-11-19	1	-0/+6
*	Large improvements in yosys-config	Clifford Wolf	2013-11-19	3	-17/+84
*	Fixed parsing of module arguments when one type is used for many args	Clifford Wolf	2013-11-19	1	-3/+10
*	Renamed temp module generated by "abc" pass from "logic" to "netlist"	Clifford Wolf	2013-11-19	2	-6/+6
*	Added additional mem2reg testcase	Clifford Wolf	2013-11-18	1	-0/+28
*	Fixed two bugs in mem2reg functionality in AST frontend	Clifford Wolf	2013-11-18	1	-4/+8
*	Added dumping of attributes in AST frontend	Clifford Wolf	2013-11-18	1	-0/+11
*	Fixed parsing of default cases when not last case	Clifford Wolf	2013-11-18	2	-12/+38
*	Fixed mem2reg for reg usage outside always block	Clifford Wolf	2013-11-18	1	-1/+1
*	Added commented-out osu025 maping commands to cmos techmap example	Clifford Wolf	2013-11-18	1	-0/+5
*	Added -v<level> option and some minor driver cleanups	Clifford Wolf	2013-11-17	3	-5/+23
*	Renamed ABCHGPULL to ABCPULL in Makefile	Clifford Wolf	2013-11-16	1	-2/+2
*	Improved building of yosys-abc	Clifford Wolf	2013-11-13	1	-1/+5
*	Fixed abc pass blif parser for constant bits	Clifford Wolf	2013-11-13	1	-18/+57
*	Fixed parsing of "parameter integer"	Clifford Wolf	2013-11-13	1	-2/+2
*	Cleanups and bugfixes in response to new internal cell checker	Clifford Wolf	2013-11-11	5	-52/+52
*	Added information on all internal cell types to internal checker	Clifford Wolf	2013-11-11	1	-0/+340
*	Call internal checker more often	Clifford Wolf	2013-11-10	4	-9/+11
*	Improved user-friendliness of "sat" and "eval" expression parsing	Clifford Wolf	2013-11-09	4	-20/+31
*	Silenced a gcc warning in spice backend	Clifford Wolf	2013-11-09	1	-1/+1
*	Added verification of SAT model to "eval -vloghammer_report" command	Clifford Wolf	2013-11-09	2	-6/+48
*	More undef-propagation related fixes	Clifford Wolf	2013-11-08	2	-0/+9
*	Fixed handling of different signedness in power operands	Clifford Wolf	2013-11-08	1	-1/+1
*	Fixed keep attribute on wires in opt_clean	Clifford Wolf	2013-11-08	1	-1/+1
*	Implemented const folding of ternary op with undef select	Clifford Wolf	2013-11-08	1	-0/+8
*	Removed debug log from const_pow()	Clifford Wolf	2013-11-08	1	-1/+0
*	Fixed handling of power operator	Clifford Wolf	2013-11-07	4	-19/+78