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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-20 11:05:58 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-20 11:05:58 +0100 |
| commit | ac2be2d892e3311b89744306e8c29445f588f590 (patch) | |
| tree | 10c83aaca2c434c7abd9875f285e3a67a707e365 | |
| parent | 19dba2561ece488543e1728ba800386943abb77c (diff) | |
| download | yosys-ac2be2d892e3311b89744306e8c29445f588f590.tar.gz yosys-ac2be2d892e3311b89744306e8c29445f588f590.tar.bz2 yosys-ac2be2d892e3311b89744306e8c29445f588f590.zip | |
Fixed name resolution of local tasks and functions in generate block
| -rw-r--r-- | README | 1 | ||||
| -rw-r--r-- | frontends/ast/simplify.cc | 18 |
2 files changed, 16 insertions, 3 deletions
@@ -292,7 +292,6 @@ Roadmap / Large-scale TODOs - yosys-bigsim: https://github.com/cliffordwolf/yosys-bigsim - Missing Verilog-2005 features to be implemented soon: - - Fix corner cases with contextual name lookup - Indexed part selects - Technology mapping for real-world applications diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 3c59ef350..57178c814 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -899,8 +899,10 @@ skip_dynamic_range_lvalue_expansion:; if ((type == AST_FCALL || type == AST_TCALL) && !str.empty()) { if (type == AST_FCALL) { - if (current_scope.count(str) == 0 || current_scope[str]->type != AST_FUNCTION) + if (current_scope.count(str) == 0 || current_scope[str]->type != AST_FUNCTION) { + current_ast_mod->dumpAst(stderr, "> "); log_error("Can't resolve function name `%s' at %s:%d.\n", str.c_str(), filename.c_str(), linenum); + } } if (type == AST_TCALL) { if (current_scope.count(str) == 0 || current_scope[str]->type != AST_TASK) @@ -1173,6 +1175,14 @@ apply_newNode: return did_something; } +static void replace_result_wire_name_in_function(AstNode *node, std::string &from, std::string &to) +{ + for (auto &it : node->children) + replace_result_wire_name_in_function(it, from, to); + if (node->str == from) + node->str = to; +} + // annotate the names of all wires and other named objects in a generate block void AstNode::expand_genblock(std::string index_var, std::string prefix, std::map<std::string, std::string> &name_map) { @@ -1202,7 +1212,11 @@ void AstNode::expand_genblock(std::string index_var, std::string prefix, std::ma if (new_name[0] != '$' && new_name[0] != '\\') new_name = prefix[0] + new_name; name_map[child->str] = new_name; - child->str = new_name; + if (child->type == AST_FUNCTION) + replace_result_wire_name_in_function(child, child->str, new_name); + else + child->str = new_name; + current_scope[new_name] = child; } } |