| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | * | | | | | | kernel: SigSpec use more const& + overloads to prevent implicit SigSpec | Eddie Hung | 2020-03-13 | 14 | -82/+96 | |
| | * | | | | | | kernel: optimise Module::remove(const pool<RTLIL::Wire*>() | Eddie Hung | 2020-03-12 | 2 | -10/+9 | |
| | * | | | | | | kernel: SigPool to use const& + overloads to prevent implicit SigSpec | Eddie Hung | 2020-03-12 | 1 | -19/+25 | |
| * | | | | | | | Bump YOSYS_VER | Claire Wolf | 2020-04-02 | 1 | -1/+1 | |
| * | | | | | | | Merge pull request #1770 from YosysHQ/claire/btor_symbols | Claire Wolf | 2020-04-02 | 1 | -36/+60 | |
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| | * | | | | | | | Improve write_btor symbol handling | Claire Wolf | 2020-03-14 | 1 | -36/+60 | |
| * | | | | | | | | Merge pull request #1765 from YosysHQ/claire/btor_info | Claire Wolf | 2020-04-02 | 1 | -9/+113 | |
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| | * | | | | | | | Add info-file and cover features to write_btor | Claire Wolf | 2020-03-13 | 1 | -9/+113 | |
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| * | | | | | | | Merge pull request #1777 from YosysHQ/claire/manyhot | Claire Wolf | 2020-04-02 | 1 | -14/+146 | |
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| | * | | | | | | | Improve ezsat onehot encoding scheme | Claire Wolf | 2020-04-02 | 1 | -14/+28 | |
| | * | | | | | | | Using LFSR counter for ezSAT::manyhot() | Claire Wolf | 2020-04-02 | 1 | -0/+118 | |
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| * | | | | | | | Merge pull request #1828 from YosysHQ/eddie/celltypes_speedup | Eddie Hung | 2020-04-01 | 4 | -31/+50 | |
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| | * | | | | | | | memory_share: fix stray brace | Eddie Hung | 2020-03-30 | 1 | -1/+0 | |
| | * | | | | | | | Code review fixes | Eddie Hung | 2020-03-30 | 2 | -3/+3 | |
| | * | | | | | | | Apply suggestions from code review | Eddie Hung | 2020-03-30 | 2 | -6/+2 | |
| | * | | | | | | | kernel: clear some more ShareWorker state | Eddie Hung | 2020-03-26 | 1 | -0/+4 | |
| | * | | | | | | | kernel: share a single CellTypes within a pass | Eddie Hung | 2020-03-18 | 4 | -31/+51 | |
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| * | | | | | | | Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor | Eddie Hung | 2020-04-01 | 4 | -10/+92 | |
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| | * | | | | | | | opt_expr: fix failing $xnor test | Eddie Hung | 2020-03-20 | 1 | -2/+17 | |
| | * | | | | | | | opt_expr: add failing $xnor test | Eddie Hung | 2020-03-20 | 1 | -1/+13 | |
| | * | | | | | | | Simplify breaking tests/arch/*/fsm.ys tests | Eddie Hung | 2020-03-20 | 2 | -7/+3 | |
| | * | | | | | | | opt_expr: fix missing brace | Eddie Hung | 2020-03-20 | 1 | -2/+4 | |
| | * | | | | | | | opt_expr: add $xor/$xnor/$_XOR_/$_XNOR_ tests | Eddie Hung | 2020-03-19 | 1 | -0/+40 | |
| | * | | | | | | | opt_expr: extend to $xnor and $_XNOR_ | Eddie Hung | 2020-03-19 | 1 | -8/+12 | |
| | * | | | | | | | opt_expr: optimise 1-bit $xor or $_XOR_ with constant input | Eddie Hung | 2020-03-19 | 1 | -1/+14 | |
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| * | | | | | | | Merge pull request #1789 from YosysHQ/eddie/opt_expr_alu | Eddie Hung | 2020-04-01 | 2 | -19/+114 | |
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| | * | | | | | | | opt_expr: add $alu tests | Eddie Hung | 2020-03-19 | 1 | -0/+63 | |
| | * | | | | | | | opt_expr: remove redundant | Eddie Hung | 2020-03-19 | 1 | -3/+0 | |
| | * | | | | | | | opt_expr: optimise $sub when both A[i] and B[i] == 1'b1 | Eddie Hung | 2020-03-19 | 1 | -9/+20 | |
| | * | | | | | | | opt_expr: optimise for identity $alu-s just like $add/$sub | Eddie Hung | 2020-03-19 | 1 | -7/+31 | |
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| * | | | | | | | Merge pull request #1844 from YosysHQ/dave/gen-source-loc | David Shah | 2020-04-01 | 1 | -0/+6 | |
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| | * | | | | | | | verilog: Add location info for generate constructs | David Shah | 2020-04-01 | 1 | -0/+6 | |
| * | | | | | | | | Merge pull request #1852 from boqwxp/cleanup_synth_ice40 | Eddie Hung | 2020-04-01 | 1 | -4/+4 | |
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| | * | | | | | | | | Fix indentation in `techlibs/ice40/synth_ice40.cc`. | Alberto Gonzalez | 2020-04-01 | 1 | -4/+4 | |
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| * | | | | | | | | Merge pull request #1849 from boqwxp/cleanup_kernel_yosys | Eddie Hung | 2020-04-01 | 1 | -14/+13 | |
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| | * | | | | | | | | Clean up pseudo-private member usage in `kernel/yosys.cc`. | Alberto Gonzalez | 2020-04-01 | 1 | -14/+13 | |
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| * | | | | | | | | Merge pull request #1850 from boqwxp/cleanup_backends | Eddie Hung | 2020-04-01 | 7 | -103/+84 | |
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| | * | | | | | | | | Update `RTLIL::id2cstr()` usage to `log_id`. | Alberto Gonzalez | 2020-04-01 | 1 | -2/+2 | |
| | * | | | | | | | | Clean up pseudo-private member usage in `backends/intersynth/intersynth.cc`. | Alberto Gonzalez | 2020-04-01 | 1 | -22/+19 | |
| | * | | | | | | | | Clean up pseudo-private member usage in `backends/blif/blif.cc`. | Alberto Gonzalez | 2020-04-01 | 1 | -15/+11 | |
| | * | | | | | | | | Clean up pseudo-private member usage in `backends/verilog/verilog_backend.cc`. | Alberto Gonzalez | 2020-04-01 | 1 | -22/+19 | |
| | * | | | | | | | | Clean up pseudo-private member usage in `backends/spice/spice.cc`. | Alberto Gonzalez | 2020-04-01 | 1 | -13/+9 | |
| | * | | | | | | | | Clean up pseudo-private member usage in `backends/edif/edif.cc`. | Alberto Gonzalez | 2020-04-01 | 1 | -23/+18 | |
| | * | | | | | | | | Clean up pseudo-private member usage in `backends/ilang/ilang_backend.cc`. | Alberto Gonzalez | 2020-04-01 | 1 | -6/+6 | |
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| * | | | | | | | | Merge pull request #1848 from YosysHQ/eddie/fix_dynslice | Claire Wolf | 2020-04-01 | 2 | -1/+13 | |
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| | * | | | | | | | ast: simplify to fully populate dynamic slicing case transformation | Eddie Hung | 2020-03-31 | 1 | -1/+1 | |
| | * | | | | | | | Add dynamic slicing Verilog testcase | Eddie Hung | 2020-03-31 | 1 | -0/+12 | |
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| * | | | | | | | Merge pull request #1761 from YosysHQ/eddie/opt_merge_speedup | Eddie Hung | 2020-03-31 | 3 | -132/+194 | |
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| | * | | | | | | opt_merge: unordered_map -> dict as per @cliffordwolf review | Eddie Hung | 2020-03-16 | 1 | -1/+1 | |
| | * | | | | | | opt_merge: speedup | Eddie Hung | 2020-03-16 | 3 | -132/+194 | |
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index : iCE40/yosys | |
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