diff options
| author | whitequark <whitequark@whitequark.org> | 2020-04-15 05:34:29 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-04-15 05:34:29 +0000 |
| commit | a143f04e7d665fa38e5b69effd66f1e56e338544 (patch) | |
| tree | a474cea4405c4b28b02b160e8059a7fb34f63992 | |
| parent | 6c16fd760b611441aaa8a9dd9ee1714c7750127a (diff) | |
| parent | 3b85b7c57a071279275f27d5547a5ad4ad2e1a44 (diff) | |
| download | yosys-a143f04e7d665fa38e5b69effd66f1e56e338544.tar.gz yosys-a143f04e7d665fa38e5b69effd66f1e56e338544.tar.bz2 yosys-a143f04e7d665fa38e5b69effd66f1e56e338544.zip | |
Merge pull request #1932 from YosysHQ/dave/cxxrtl-unclocked-read
cxxrtl: Fix handling of unclocked memory read ports
| -rw-r--r-- | backends/cxxrtl/cxxrtl.cc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/backends/cxxrtl/cxxrtl.cc b/backends/cxxrtl/cxxrtl.cc index 3263f03fd..d1a855bf0 100644 --- a/backends/cxxrtl/cxxrtl.cc +++ b/backends/cxxrtl/cxxrtl.cc @@ -871,7 +871,8 @@ struct CxxrtlWorker { dump_sigspec_rhs(cell->getPort(ID(ADDR))); f << ", " << memory->start_offset << ", " << memory->size << ");\n"; if (cell->type == ID($memrd)) { - if (!cell->getPort(ID(EN)).is_fully_ones()) { + bool has_enable = cell->getParam(ID(CLK_ENABLE)).as_bool() && !cell->getPort(ID(EN)).is_fully_ones(); + if (has_enable) { f << indent << "if ("; dump_sigspec_rhs(cell->getPort(ID(EN))); f << ") {\n"; @@ -930,7 +931,7 @@ struct CxxrtlWorker { f << " = value<" << memory->width << "> {};\n"; dec_indent(); f << indent << "}\n"; - if (!cell->getPort(ID(EN)).is_fully_ones()) { + if (has_enable) { dec_indent(); f << indent << "}\n"; } |